ISD94100 Series Technical Reference Manual
Sep 9, 2019
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of shifting a byte. When I
2
C is in a defined state and the serial interrupt flag (SI) is set, data in
I2C_DAT [7:0] remains stable. While data is being shifted out, data on the bus is simultaneously
being shifted in; I2C_DAT [7:0] always contains the last data byte presented on the bus.
The acknowledge bit is controlled by the I
2
C hardware and cannot be accessed by the CPU. Serial
data is shifted into I2C_DAT [7:0] on the rising edges of serial clock pulses on the SCL line. When
a byte has been shifted into I2C_DAT [7:0], the serial data is available in I2C_DAT [7:0], and the
acknowledge bit (ACK or NACK) is returned by the control logic during the ninth clock pulse. In
order to monitor bus status while sending data, the bus data will be shifted to I2C_DAT[7:0] when
sending I2C_DAT[7:0] to bus. In the case of sending data, serial data bits are shifted out from
I2C_DAT [7:0] on the falling edge of SCL clocks, and is shifted to I2C_DAT [7:0] on the rising edge
of SCL clocks. The Figure 6.13-26 shows I
2
C Data Shifting Direction.
I2DAT.7 I2DAT.6 I2DAT.5 I2DAT.4 I2DAT.3 I2DAT.2 I2DAT.1 I2DAT.0
I
2
C
Data Register:
shifting direction
Figure 6.13-26 I
2
C Data Shifting Direction
6.13.5.4.4
Control Register (I2C_CTL)
The CPU can be read from and written to I2C_CTL [7:0] directly. When the I
2
C port is enabled by
setting I2CEN (I2C_CTL [6]) to high, the internal states will be controlled by I2C_CTL and I
2
C logic
hardware.
There are two bits are affected by hardware: the SI bit is set when the I
2
C hardware requests a
serial interrupt, and the STO bit is cleared when a STOP condition is present on the bus. The STO
bit is also cleared when I2CEN = 0.
Once a new status code is generated and stored in I2C_STATUS, the I
2
C Interrupt Flag bit SI
(I2C_CTL [3]) will be set automatically. If the Enable Interrupt bit INTEN (I2C_CTL [7]) is set at this
time, the I
2
C interrupt will be generated. The bit field I2C_STATUS[7:0] stores the internal state
code, the content keeps stable until SI is cleared by software.
6.13.5.4.5
Status Register (I2C_STATUS)
I2C_STATUS [7:0] is an 8-bit read-only register. The bit field I2C_STATUS [7:0] contains the status
code and there are 26 possible status codes. All states are listed in Table 6.13.5-3.When
I2C_STATUS [7:0] is F8H, no serial interrupt is requested. All other I2C_STATUS [7:0] values
correspond to the defined I
2
C states. When each of these states is entered, a status interrupt is
requested (SI = 1). A valid status code is present in I2C_STATUS[7:0] one cycle PCLK after SI set
by hardware and is still present one cycle PCLK after SI reset by software.
In addition, the state 00H stands for a Bus Error, which occurs when a START or STOP condition
is present at an incorrect position in the I
2
C format frame. A Bus Error may occur during the serial
transfer of an address byte, a data byte or an acknowledge bit. To recover I
2
C from bus error, STO
should be set and SI should be cleared to enter Not Addressed Slave mode. Then STO is cleared
to release bus and to wait for a new communication. The I
2
C bus cannot recognize stop condition
during this action when a bus error occurs.
