ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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MCLKDIV
Master Clock Divider
If MCLKEN is set to 1, I
2
S controller will generate master clock for external audio devices.
The frequency of master clock, f
MCLK
, is determined by the following expressions:
If MCLKDIV >= 1,.
MCLKDIV
2
_
_
2
×
=
f
f
src
clock
s
i
MCLK
If MCLKDIV = 0,.
f
f
src
clock
s
i
MCLK
_
_
2
=
where
f
src
clock
s
i
_
_
2
is the frequency of I
2
S peripheral clock source, which is defined in the
clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times
sampling clock rate.
