ISD94100 Series Technical Reference Manual
Sep 9, 2019
Page
744
of 928
Rev1.09
IS
D
9
410
0
S
ER
IE
S
T
E
C
HN
ICA
L
RE
F
E
RE
NCE
M
AN
U
AL
Note:
This bit will be cleared by writing 1 to it.
[18]
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
0 = The valid data count within the transmit FIFO buffer is larger than the setting value of
TXTH.
1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting
value of TXTH.
Note:
If TXTHIEN = 1 and TXTHIF = 1, the SPI/I
2
S controller will generate a SPI interrupt
request.
[17]
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
0 = Transmit FIFO buffer is not full.
1 = Transmit FIFO buffer is full.
[16]
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
0 = Transmit FIFO buffer is not empty.
1 = Transmit FIFO buffer is empty.
[15]
I2SENSTS
I
2
S Enable Status (Read Only)
0 = The SPI/I
2
S control logic is disabled.
1 = The SPI/I
2
S control logic is enabled.
Note:
The SPI peripheral clock is asynchronous with the system clock. In order to make
sure the SPI/I
2
S control logic is disabled, this bit indicates the real status of SPI/I
2
S control
logic for user.
[14:13]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[12]
RXTOIF
Receive Time-out Interrupt Flag
0 = No receive FIFO time-out event.
1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64
SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave
mode. When the received FIFO buffer is read by software, the time-out status will be cleared
automatically.
Note:
This bit will be cleared by writing 1 to it.
[11]
RXOVIF
Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be
set to 1.
Note:
This bit will be cleared by writing 1 to it.
[10]
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting
value of RXTH.
1 = The valid data count within the receive FIFO buffer is larger than the setting value of
RXTH.
Note:
If RXTHIEN = 1 and RXTHIF = 1, the SPI/I
2
S controller will generate a SPI interrupt
request.
[9]
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
0 = Receive FIFO buffer is not full.
1 = Receive FIFO buffer is full.
[8]
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
0 = Receive FIFO buffer is not empty.
1 = Receive FIFO buffer is empty.
[7:5]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
