ISD94100 Series Technical Reference Manual
Sep 9, 2019
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DPWM FIFO Data Input Register (DPWM_FIFO)
Register
Offset
R/W Description
Reset Value
DPWM_FIFO
0x0C
W
DPWM FIFO Data Input Register
0x0000_0000
31
30
29
28
27
26
25
24
FIFO
23
22
21
20
19
18
17
16
FIFO
15
14
13
12
11
10
9
8
FIFO
7
6
5
4
3
2
1
0
FIFO
Bits
Description
[31:0]
FIFO
FIFO Data Input Register
DPWM contains 32 words (32x32 bit) data buffer for data transmit. A write to this register
pushes data onto the FIFO data buffer and increments the write pointer. This is the address
that PDMA writes audio data to. The remaining word number is indicated by FIFOPTR
(DPWM_STATUS[8:4]).
