ISD94100 Series Technical Reference Manual
Sep 9, 2019
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6.2.2.5 Watchdog Timer Reset (WDT)
A Watchdog reset can be identified by checking WDTRF bit (SYS_RSTSTS[2]).
6.2.2.6 CPU Lockup Reset
CPU enters lockup state after CPU produces hardfault at hardfault handler. This is the result of the
CPU being locked because of an unrecoverable exception, following the activation of the
processor’s built in system state protection hardware. When chip is in debug mode, the CPU lockup
reset will be ignored.
6.2.2.7 CPU Reset, CHIP Reset and MCU Reset
A CPU Reset only resets the Cortex®-M4 core, while all other peripherals keep the state as is.
Writing 1 to CPURST bit(SYS_IPRST0[1]) triggers a CPU reset.
CHIP Reset acts the same as Power-on Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0. Writing 1 to CHIPRST bit
(SYS_IPRST0[1]) triggers a CHIP Reset.
MCU Reset is similar to CHIP Reset as the only difference is that MCU Reset does not reload
BS(FMC_ISPCTL[1]) from CONFIG0; so where device will boot from (APROM or LDROM) still
depends on the old value in BS(FMC_ISPCTL[1]). Writing 1 to SYSRESETREQ bit (AIRCR[2])
triggers a MCU Reset.
6.2.2.8 Reset Flag
After wake-up or reset from each power modes, reset flag in SYS_RSTSTS register will take effect
when system return Normal mode. Table 6.2.2-2 shows the LVRF (SYS_RSTSTS[3]), PINRF
(SYS_RSTSTS[1]) and PORF (SYS_RSTSTS[0]) effect when wake-up or reset from different power
modes. Note that LVR function cannot be used in DPD mode.
Conditions
Flag
Power
Mode
Power-on
Reset
Low
Voltage
Reset
nRESET
Reset
Wakeup
LVRF
SYS_RSTSTS[3]
PINRF
SYS_RSTSTS[1]
PORF
SYS_RSTSTS[0]
Normal /
Idle
V
-
-
-
V
V
V
-
V
-
-
V
-
-
-
-
V
-
-
V
-
SPD0/1
V
-
-
-
V
V
V
-
V
-
-
V
V
V
-
-
V
-
-
V
V
-
-
-
V
-
V
V
DPD
V
-
-
-
V
V
V
-
-
V
-
-
V
V
-
-
-
V
V
V
V
Table 6.2.2-2 Reset Flag Table
6.2.3
System Power Distribution
ISD94100 series device power distribution is divided into:
Analog power from AV
DD
and AV
SS
: provides the power for analog components
operation.
