Nvis 5586A
Nvis Technologies Pvt. Ltd.
9
instructions from the instruction system byte queue. Both units operate asynchronously to
give the 8086 an overlapping instruction fetch and execution mechanism which is called as
Pipelining
. This results in efficient use of the system bus and system performance. BIU
contains Instruction queue, Segment registers, Instruction pointer, and Address adder. EU
contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag
register.
Bus Interface Unit:
It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is
responsible for performing all external bus operations.
Specifically it has the following functions:
Instruction fetching,
Instruction queuing,
Operand fetch and storage,
Address relocation and Bus control.
The BIU uses a mechanism known as an instruction stream queue to implement pipeline
architecture
.
This queue permits prefetch of up to six bytes of instruction code. Whenever the
queue of the BIU is not full, it has room for at least two more bytes and at the same time the
EU is not requesting it to read or write operands from memory, the BIU is free to look ahead
in the program by prefetching the next sequential instruction. These prefetching instructions
are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a
single memory cycle. After a byte is loaded at the input end of the queue, it automatically
shifts up through the FIFO to the empty location nearest the output.
The EU accesses the queue from the output end. It reads one instruction byte after the other
from the output of the queue. If the queue is full and the EU is not requesting access to
operand in memory, these intervals of no bus activity, which may occur between bus cycles,
are known as
idle state
.
If the BIU is already in the process of fetching an instruction when the EU request it to read
or write operands from memory or I/O, the BIU first completes the instruction fetch bus
cycle before initiating the operand read / write cycle.
The BIU also contains a dedicated adder which is used to generate the 20 bit physical address
that is output on the address bus. This address is formed by adding an
appended 16 bit
segment address and a 16 bit offset address.
For example, the physical address of the next instruction to be fetched is formed by
combining the current contents of the code segment CS register and the current contents of
the instruction pointer IP register.
Summary of Contents for 5586A
Page 2: ...Nvis 5586A Nvis Technologies Pvt Ltd 2...
Page 23: ...Nvis 5586A Nvis Technologies Pvt Ltd 23 Memory Read Timing in Maximum Mode...
Page 30: ...Nvis 5586A Nvis Technologies Pvt Ltd 30...
Page 48: ...Nvis 5586A Nvis Technologies Pvt Ltd 48 Diagram of module RESET power Instruction Set Note...
