Table 23. Clock configuration jumper settings
Clock In
000
001
010
011
100
101
110
111
Config 1
Config 2
Config 3
Config 4
Config 5
Config 6
Config 7
Config 8
J5:2-3
J5:2-3
J5:2-3
J5:2-3
J5:1-2
J5:1-2
J5:1-2
J5:1-2
J14:2-3
J14:2-3
J14:1-2
J14:1-2
J14:2-3
J14:2-3
J14:1-2
J14:1-2
J15:2-3
J15:1-2
J15:2-3
J15:1-2
J15:2-3
J15:1-2
J15:2-3
J15:1-2
CLK01
CLK01
CLK01
CLK01
CLK01
CLK01
CLK01
CLK01
CLK01
CLK23
CLK23
CLK23
CLK23
CLK23
CLK01
CLK01
CLK01
CLK01
CLK45
CLK45
CLK45
CLK01
CLK01
CLK45
CLK45
CLK01
CLK01
CLk67
CLk67
CLK45
CLk67
CLK01
CLk67
CLK45
CLk67
CLK01
When using the 8CH-DMIC board with the i.MX RT600 EVK (MIMXRT685-AUD-EVK) board, the codec device
on the MIMXRT685-AUD-EVK board must have the MCLK clock frequency reduced to 4.096 MHz and the Input
Sample Rate (LRCK) must be reduced to 16 kHz. This change in clock frequency and LRCK maintains compliance
of the MIMXRT685-AUD-EVK board with mandatory FCC and EU EMC limitations. Failure to do so will cause the
MIMXRT685-AUD-EVK board to exceed FCC and EU EMC limits. It is the responsibility of the end user to comply
with this requirement. The end user assumes all responsibility for not complying with this requirement.
NOTE
NXP Semiconductors
Functional Description
Eight-channel DMIC Board User Manual, Rev. 2, 15 March 2022
User Guide
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