11 Default switch settings
The dual inline package (DIP) switches are used to configure or power up the boot source and to reset some bit settings. This
table shows the detailed switch description for the AFD4400-RDB.
Table 3. Default DIP switch configurations
Switch
Default setting
[OFF = 0, ON = 1]
Switch name
Description
SW4[8]
OFF
REF_FREQ
Maps to the REF_FREQ switch of the AFD4400-RDB. It is
used by the boot code for the PLL programming.
OFF: 122.88 MHz frequency is enabled.
ON: 125 MHz frequency is enabled.
SW4[7]
ON
DFE_SJC_MOD_B
Maps to the SJC_MOD_B switch of the AFD4400-RDB. It
selects the system JTAG controller (SJC) as a primary JTAG
TAP.
OFF: JTAG pins connect to SJC.
ON: JTAG pins connect to debug access port (DAP).
SW4[6]
OFF
DFE_VSPJTAG_SEL
Maps to the JTAG_VSP_SEL switch of the AFD4400-RDB. It
enables the VSPA JTAG on the GPIOD[4:8] pins of the
AFD4400 processor.
OFF: VSPA JTAG on GPIOD[4:8] is disabled.
ON: VSPA JTAG on GPIOD[4:8] is enabled.
SW4[5]
OFF
SP1_POR_DIPSW
Spare
SW4[4]
OFF
PO2VDD_EN
Enables the POVDD2 for the fuse programming of the
AFD4400.
OFF: POVDD2 is disabled.
ON: POVDD2 is enabled.
SW4[3]
OFF
PO1VDD_EN
Enables the POVDD1 for the fuse programming of the
AFD4400.
OFF: POVDD1 is disabled.
ON: POVDD1 is enabled.
SW4[2]
ON
GVDD5_3V3_EN
Selects the GVDD5 voltage.
OFF: GVDD5 is 1.8 V.
ON: GVDD5 is 3.3 V.
SW4[1]
ON
GVDDa_3V3_EN
Selects the GVDDa voltage.
OFF: GVDDa is 1.8 V.
ON: GVDDa is 3.3 V.
SW5[8]
OFF
JCPLL_REF_SEL
Maps to the REFSEL of AD9525 JCPLL and selects the
reference clock for JCPLL.
OFF: REFA is selected.
ON: REFB is selected.
Table continues on the next page...
Default switch settings
AFD4400 Reference Design Board Quick Start, Rev. 0, 07/2015
12
Freescale Semiconductor, Inc.
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