NXP Semiconductors
KTFRDMHB2001FEVMUG
FRDM-HB2001FEVM evaluation board
KTFRDMHB2001FEVMUG
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User guide
Rev. 1.0 — 25 May 2016
25 / 35
6.2.2 Parallel control
Figure 16. Parallel control description
Direction
:
•
Forward
: Current flowing through OUT1 to OUT2
•
Reverse
: Current flowing through OUT2 to OUT1
Recirculation
:
•
High-side
: Freewheel-High (both high-side FETs turned on) during PWMing
•
Low-side
: Freewheel-Low (both low-side FETs turned on) during PWMing (only valid
for Half-Bridge mode)
ENBL
:
•
Yes
: ENBL is logic HIGH, the H-Bridge is operational
•
No
: ENBL is logic LOW, the H-Bridge outputs are tri-stated and placed in Sleep mode
DIS
:
•
DIS is logic HIGH, both OUT1 and OUT2 are tri-stated
•
DIS is logic LOW, both OUT1 and OUT2 are enabled
PWM Freq
:
•
Enter PWM frequency up to 20000 Hz
Duty Cycle
:
•
Select PWM duty cycle from 10 to 90 %
Start
:
•
After selection of parallel control configuration, press
Start
to activate the outputs
