NXP Semiconductors
UM11620
FRDMGD3160XM3EVM half-bridge evaluation board
4.4.3 Power supply and jumper configuration
Figure 5. Power supply and jumper configuration
Jumper
Position
Function
1-2
dead time fault protection enabled (low side)
PWMALTL (J9)
2-3
dead time fault protection disabled (use for short-circuit testing)
1-2
dead time fault protection enabled (high side)
PWMALTH (J10)
2-3
dead time fault protection disabled (use for short-circuit testing)
open
VCCREG controls gate voltage
VCCH and VCCL
(R25 and R46)
closed
VCC and VCCREG are tied together
open
internally regulated supply derived from VSUP
VDDH and VDDL
(R28 and R47)
closed
VSUP = VDD for 5 V or 3.3 V operation depending on the part number
1-2
chip select for normal operation
CSB (J17)
2-3
chip select for daisy chain operation
closed
normal operation
MOSI (J19)
open
daisy chain operation
1-2
normal operation
MISO (J21)
2-3
daisy chain operation
Table 4. Jumper definitions
UM11620
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User guide
Rev. 1 — 10 June 2021
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