KIT33905 Evaluation Boards
, Rev. 2.0
Freescale Semiconductor
9
Hardware Configuration
6.4
Power Supply and Input/Output Connectors
The three pin terminal block (J9) serves as the main power terminal to supply a minimum of 5.5 V to
operate KIT33905D5EKEVBE/KIT33905BD3EVBE.
The CAN, LIN1, and LIN2 bus signals are accessible through the three pin terminal blocks J12, CON1,
and CON2 respectively.
6.5
Connector J1 – External Control
Pin #
Pin Name
Description
1
MISO
SPI data sent to the MCU. When the CS is high, MISO is high-impedance
2
MOSI
SPI data received by the device
3
SCLK
Clock input for the Serial Peripheral Interface (SPI) of the device
4
CSB
Chip select pin for the SPI. When the CS is low, the device is selected. In Low
Power mode with VDD ON, a transition on CS is a wake-up condition
5
TXDC_I
CAN bus transmit data input. Internal pull-up to VDD
6
RXDC
CAN bus receive data output
7
I_WAKE_I
Active high input to enable on-board FET to create a 5.0 mA load on VDD
8
N/C
Not Connected
9
VDD
5.0/3.3 V output of the main regulator for the Microcontroller supply
10
INTB_I
This output is asserted low when an enabled interrupt condition occurs. The output
is a push-pull structure
11
RSTB_I
This is the device reset output whose main function is to reset the MCU. It has an
internal pull-up to VDD. The reset input voltage is also monitored in order to detect
external reset and safe conditions
12
TXDL1
LIN1 bus transmit data input. Includes an internal pull-up resistor to VDD
13
RXDL1
LIN1 bus receive data output
14
TXDL2
LIN bus transmit data input. Includes an internal pull-up resistor to VDD
15
RXDL2
LIN2 bus receive data output
16
GND
Ground termination
