M5251C3 Evaluation Board Users Guide, Rev. 0
Freescale Semiconductor
3-5
3.1.10
TA Generation
The processor starts a bus cycle by asserting -CSx with the other control signals. The processor then waits
for a transfer acknowledgment (-TA) either from within (Auto acknowledge - AA mode) or from the
externally addressed device before it can complete the bus cycle. -TA is used to indicate the completion of
the bus cycle. It also allows devices with different access times to communicate with the processor
properly (that is, asynchronously). The MCF5251 processor, as part of the chip-select logic, has a built-in
mechanism to generate -TA for all external devices which do not have the capability to generate this signal.
For example the Flash ROM cannot generate a -TA.signal. The chip-select logic is programmed by the
dBUG ROM Monitor to generate -TA internally after a pre-programmed number of wait states.
3.1.11
Wait State Generator
The Flash ROM and SDRAM on the board may require some adjustments to the cycle time of the
processor to make them compatible with the processor’s external bus speed. To extend the CPU bus cycles
for the slower devices, the chip-select logic of the MCF5251 processor can be programmed to generate an
internal -TA after a given number of wait states. See
for information about the address space of
the memory and refer to the manufacturer’s specification for wait state requirements of the SDRAM and
Flash ROM.
3.1.12
SDRAM
The M5251C3 has one 64-Mbit device on the board, in a 16-bit wide data bus configuration. The
MCF5251 processor supports one bank of SDRAM, which on this board is represented by SDRAM
device, (U12). These are connected to the MCF5251 to provide 4Mx16 of memory.
3.1.13
Flash ROM
There is one 2-Mbyte Flash ROM on the M5251C3, (U11).
The board is shipped with one AMD Am29LV160DB, 2-Mbyte Flash ROM. The first 256 Kbytes of the
Flash contains the ROM Monitor firmware dBUG. The remaining Flash memory is available to the user.
The MCF5251 chip-select logic can be programmed to generate the -TA for -CS0 signal after a certain
number of wait states (that is, auto-acknowledge mode). The dBUG monitor programs this parameter to
be six wait-states.
3.2
Serial Communication Channels
The M5251C3 offers five types of serial communications channels. They are discussed in this section.
3.2.1
MCF5251 UARTs
The MCF5251 device has three built-in UARTs, each with its own software programmable baud rate
generator. UART0 is the ROM Monitor to Terminal output. The ROM Monitor programs the interrupt
level for UART0 to Level 3, priority 2 and autovector mode of operation. See the
MCF5251 Reference
Manual
for programming the UARTs and their register maps.
Summary of Contents for freescale M5251C3
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