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Datasheet of MCIMX53SMD - TABLET SABRE PLATFORM MCIMX53
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MCIMX53SMD Board Hardware User’s Guide, Rev. 0
Freescale Semiconductor
5.15.
Debug UART Serial Port (Debug Board)
The i.MX53 processor has five independent UART Ports (UART1 – UART5). By default, the processor will boot
using UART1 to output serial debugging information, specifically on pins CSI0_DAT10 (pin R5) and CSI0_DAT11
(pinT2). These two pins are outputted from the NVCC_CSI module, which is pulled up to 1.8V on the
MCIMX53SMD board. The MCIMX53SMD board uses two single-direction level shifters (U40, U41) to convert
the UART Transmit and Receive signal to a 3.3V logic signal. The level shifted signals are sent to a low cost,
RS232 transceiver, which reformats the signals to the correct voltages and drives the signals. The resulting
cable ready signals are then connected to the RS232 Debug connector. No RTS or CTS signals are sent from the
processor to the Debug connector, since these signals are commonly ignored by most applications. The
required terminal settings to receive debug information during the boot cycle are shown in
Table 5-7
.
Table 5-7.
Terminal Setting Parameters
If the developer wishes to use the Debug UART connector in software as an Applications Connector, the
MCIMX53SMD board can support this using a Null Modem Adapter. The adapters are readily available from
most cable and electronics stores at a low cost.
5.16.
JTAG Operations (Debug Board)
The i.MX53 processor accepts five JTAG signals from an attached debugging device on dedicated pins. A sixth
pin on the processor accepts a HW board configured input, specific to the MCIMX53SMD board. The five JTAG
signals used by the processor are:
JTAG_TCK
TAP Clock
JTAG_TMS
TAP Machine State
JTAG_TDI
TAP Data In
JTAG_TDO
TAP Data Out
JTAG_nTRST
TAP Reset Request (Active Low)
The TAP Clock signal is provided by the attached debugging device that serves as a reference for data
exchange between the debugging device and the processor. The TAP Machine State is a logical signal provided
by the debugging device to let the processor (or target) know which state to enter next. As per JTAG
specifications, there are two states, one of which can be selected with a ‘high’ signal and other with a ‘low’
signal. The TAP Data In and TAP Data Out signals are used only for data transfer.
The Active Low TAP Reset Request is initiated by the debugging device and it resets the TAP (JTAG) module
within the processor. This enables the debugging device to reset the internal processor JTAG module, if
required, without affecting rest of the processor. The system JTAG reset signal provided by the attached
debugging device does not go to the JTAG module of the processor, but goes to the external processor reset
circuitry. This will reset the entire i.MX53 processor, but not the power rails.
The JTAG_MOD pin used by the JTAG module of the i.MX53 processor determines what portion of the i.MX53
processor is connected to the JTAG debugging device. In the pull-down mode (default on the MCIMX53SMD
board), all the i.MX53 TAPs (SJC, SDMA, ARM) are connected to the debugging device in a daisy chain
connection. If the JTAG_MOD pin is pulled high, then, the attached debugging device can only access the SJC
TAP.
Data Rate
115,200 Baud
Data bits
8
Parity
None
Stop bits
1
Flow Control
None
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