ERR005382
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors
65
Description:
The LDM PC ^ instructions with base address register write-back might be counted twice in the
PMU event 0x0A, which is counting the number of exception returns.
The associated PMUEVENT[11] signal is also affected by this erratum, and might be asserted
twice by a single LDM PC ^ instruction with base address register write-back.
Projected Impact:
Due to the erratum, the count of exception returns is imprecise. The error rate depends on the ratio
between exception returns of the form LDM PC ^ with base address register write-back and the
total number of exceptions returns.
Workarounds:
There is no workaround to this erratum.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround not implemented in Linux BSP. Functionality or mode of operation in which
the erratum may manifest itself is not used.The Freescale Linux BSP does not support this optional
profiling feature. Users may add support for this profiling feature as required, but should ensure
the multiple errata impacting the ARM PMU (Performance Monitoring Unit) are considered
especially for multi-core usage.
ERR005382
ARM/MP: 775419—PMU event 0x0A (exception return) might count
twice the LDM PC ^ instructions with base address register
write-back
