ERR005188
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
166
NXP Semiconductors
Description:
Under the condition where the core enters L1 and is then directed to immediately exit due to a
pending TLP transmission, the LTSSM misses the PhyStatus pulse because of the gated core_clk
in clk_rst.v.
Scenario Setup:
• LTSSM enters L1 and indicates to the PHY to change Powerdown to P1.
• Core immediately gets a wake-up event and wants to exit from L1. To make the transition into
Recovery, the core needs to receive PhyStatus back from the PHY
• The PHY changes Powerdown to P1 and asserts PhyStatus back to Core.
• LTSSM moves to Recovery state and indicates to the PHY to change Powerdown to P0
• core_clk is gated off immediately after LTSSM enters Recovery. This can happen as a result of
the logic in the clk_rst module that is performing glitch-less clock switch on aux_clk
• The PHY changes Powerdown to P0 and asserts PhyStatus back to core.
• LTSSM misses the PhyStatus because core_clk is still gated off by the clk_rst module.
Projected Impact:
The core’s LTSSM does not proceed to exit from Recovery and is awaiting a Powerdown indication
from the PHY. The LTSSM will eventually timeout and move to Detect state and resume operation
by initiating receiver detection.
Workarounds:
Increase the programming of the “Low Power Entrance Count” field of the “Port Force Link
Register” (maximum is 255). This delays the entry into L1 and prevents the problem from
occurring. The “Low Power Entrance Count” field is for Power Management state to wait for these
many clock cycles for the associated completion of a configuration write to D-state register to go
low power. The longer delay is to ensure that the completion TLP can be sent by the core to avoid
immediate waking-up after entering L1.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround not implemented in Linux BSP. Functionality or mode of operation in which
the erratum may manifest itself is not used.
ERR005188
PCIe: The PCIe Controller cannot exit successfully L1 state of LTSSM
when the Core Clock is removed
