ERR003730
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
34
NXP Semiconductors
Description:
Under very rare circumstances, a deadlock can happen in the processor when it is handling a
minimum of seven PLD instructions, shortly followed by one LDM to an uncacheable memory
location.
The LDM is treated as uncacheable in the following cases:
• The LDM is performed while the Data Cache is OFF
• The LDM is targeting a memory region marked as Strongly Ordered, Device, Normal Memory
Non-Cacheable, or Normal Memory Write-Through
• The LDM is targeting a memory region marked as Shareable Normal Memory Write-Back, and
the CPU is in AMP mode.
Conditions:
The code sequence that exhibits this erratum requires at least seven PLDs, shortly followed by one
LDM, to an uncacheable memory region. The erratum happens when the LDM appears on the AXI
bus before any of the seven PLDs. This can possibly happen if the first PLD is a miss in the
micro-TLB; in that case, it needs to perform a TLB request which might not be serviced
immediately because the mainTLB is already performing a Page Table Walk for another resource
(for example, instruction side), or because the PLD request itself to the mainTLB is missing and
causing a Page Table Walk.
Also note that the above conditions are not sufficient to recreate the failure, as additional rare
conditions on the internal state of the processor are necessary to exhibit the errata.
Projected Impact:
The erratum might create a processor deadlock. However, the conditions that are required for this
to occur are extremely unlikely to occur in real code sequences.
Workarounds:
The primary workaround might be to avoid the offending code sequence, that is, not to use
uncacheable LDM when making intensive use of PLD instructions.
In case the above workaround cannot be done, another workaround for this erratum can be to set
bit[20] in the undocumented Control register, which is placed in CP15 c15 0 c0 1.
This bit needs to be written with the following Read/Modify/Write code sequence:
MRC p15,0,r0,c15,c0,1
ORR r0,r0,#0x00100000
MCR p15,0,r0,c15,c0,1
Setting this bit causes all PLD instructions to be treated as NOPs, with the consequence that code
sequences usually using the PLDs, such as the memcpy() routine, might suffer from a visible
performance drop.
ERR003730
ARM: 743623—Bad interaction between a minimum of seven PLDs
and one Non-Cacheable LDM can lead to a deadlock
