HW TX deadline misses: 0 (0.000%)
SW TX deadline misses: 5 (0.050%)
The path delay has increased, but that is because now it contains the time spent by the packets blocked on the switch waiting
for gate 6 to open.
The HW RX deadline delta now has a new meaning, since in the last example (with 802.1Qbv enabled on the switch), the gate
acts as a barrier and eliminates the jitter in HW TX timestamps, which is induced by scheduling latencies in the sender's operating
system. Generally speaking, the jitter of the sender is eliminated by the first switch upon packet admission into the TSN network.
The effect is that the receiver sees a packet stream with low jitter.
The path delay can be reduced by decreasing the advance time. It is configured in such a way that the packets arrive on the
switch prior to the gate opening, which depends on the jitter of the sender. Minimizing the TX jitter is outside the scope of this
demonstration.
8.2.4 NETCONF usage
YANG models for the SJA1105 ports using the DSA driver are not supported as of this release.
For YANG models supporting the sja1105-tool, please check the documentation from previous OpenIL releases.
NXP Semiconductors
TSN
Open Industrial User Guide, Rev. 1.8, 05/2020
User's Guide
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