NXP Semi
conductor
s
Designing a
Hi-Spe
ed US
B hos
t PCI adapter using
ISP1562/63
AN10050
Applic
atio
n n
o
te
A
N10
050
_
4
Rev. 04 —
1 No
vember
2007
10 of 1
8
© NX
P
B.
V. 2
007.
A
ll r
igh
ts
r
es
er
v
ed.
DVAUX
C20
0.1
μ
F
C17
C22
0.1
μ
F
0.001
μ
F
+3.3 V
Should be placed
as close as
possible to pin 98
Should be placed
as close as
possible to pin 55
C21
0.1
μ
F
U2A
A1
A3
GND
VCC
NC/WP
SCL
SDA
AT24C01A-2.7
U2
A0
A1
A3
GND
VCC
NC/WP
SCL
SDA
AT24C01A-2.7
+3.3 V
C9
0.1
μ
F
R2
0
Ω
R4
R5
R3
0
Ω
R6
0
Ω
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Should be placed
as close as
possible to pin 3
C38
0.1
μ
F
All capacitors should be placed as close as possible
to the corresponding power pins.
AVAUX
+3.3 V
C49
1 nF
C50
1 nF
C51
1 nF
C31
C32
C33
0.1
μ
F
0.1
μ
F
0.1
μ
F
0.1
μ
F
C34
C35
C36
C37
0.1
μ
F
1 nF
1 nF
0.1
μ
F 0.1
μ
F 0.1
μ
F
0.1
μ
F
0.1
μ
F
C10
4.7
μ
F
C23
C24
C25
C26
C27
C30
4.7
μ
F
+
+
+3.3 V
JP1
HEADER 3
3.3 VAUX
1
2
3
BLM21PG221SN1
C28
C60
C59
0.1
μ
F
470 pF
47
μ
F / 6.3 V
AVAUX
D3 LED
R1
330
Ω
DVAUX
All capacitors should be placed
as close as possible to the
corresponding ferrite bead
AVAUX
BLM18PG121SN1
FB2
+
FB 1
C29
C19
0.1
μ
F
1 nF
C61
+
4.7
μ
F / 6.3 V
SCL
SDA
96
97
SCL
SDA
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
AD[9]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]
AD0
AD1
AD2
AD4
AD3
70
69
68
67
66
65
AD5
AD6
63
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
62
59
57
56
54
53
52
51
50
34
33
31
30
29
28
27
26
22
21
20
15
14
13
12
10
C/BE#[0]
C/BE#[1]
C/BE#[2]
C/BE#[3]
C/BE0#
C/BE1#
C/BE2#
C/BE3#
60
48
35
23
78
87
OC1#
OC2#
PWE1#
PWE2#
DM1
DM2
DP1
DP2
79
88
83
90
85
92
OC1_N
OC2_N
PWE1_N
PWE2_N
DM1
DM2
DP1
DP2
RREF
GNDA
XTAL1
XTAL2
81
80
74
75
R7
12 k
Ω
/ 1 %
C62
C63
OSC1
12 MHz
OC1#
OC2#
PWE1#
PWE2#
DM1
DM2
DP1
DP2
PME#
PCICLK
RST#
PAR
SERR#
PERR#
CLKRUN#
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
IDSEL
GNT#
REQ#
INTA#
PME#
PCICLK
RST#
PAR
SERR#
PERR#
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
IDSEL
GNT#
REQ#
INTA#
PME#
PCICLK
RST#
PAR
SERR#
PERR#
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
IDSEL
GNT#
REQ#
INTA#
99
7
5
47
45
44
42
41
39
38
37
36
24
8
9
4
C/BE0#
C/BE1#
C/BE2#
C/BE3#
U1
ISP1562ESP
A
UX1V18
A
UX1V18
REG1V18
REG1V18
REG1V18
V
I(VREG3V3)
V
CC(I/O)
V
CC(I/O
)
V
CC(I/O)
V
CC(I/O)
V
CC(I/O)
V
I(V
A
UX3V3)
V
CC(I/O)_A
UX
V
CC(I/O)_A
UX
V
CC(I/O)_A
UX
V
DD
A_A
UX
V
DD
A_A
UX
2
73
18
43
58
16
11
25
40
55
71
3
77
98
100
86
93
GND
A
GND
A
GND
A
GND
A
GND
A
GNDD
GNDD GNDD
GNDD
GNDD
GNDD GNDD
GNDD
GND
A
GND
A
GND
A
GND
A
1
17 46
61
72
6
19
32
49
64
76
94 95
82
89
84
91
AD[31:0]
22 pF
22 pF
1 k
Ω
R8
4.7 k
Ω
4.7 k
Ω
DVAUX
DVAUX
DVAUX
A0
DVAUX
DVAUX
FB3
BLM18PG121SN1
C18
0.001
μ
F
FB3 is optional. Can be directly tied to ground.
Fig 2. ISP1562 eval board schematic – ISP1562
