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NXP Semiconductors 

AN10050

 

Designing a Hi-Speed USB host PCI adapter using ISP1562/63

AN10050_4 

© NXP B.V.  2007. All rights reserved.

Application note 

Rev. 04 — 1 November 2007 

6 of 18

are defined on pins 96 (SCL) and 97 (SDA) of the ISP1562, and pins 122 (SCL) and 123 
(SDA) of the ISP1563, respectively. When not in use, these signals must be connected to 
ground using a pull-down resistor, typically 10 k

Ω

3.5  Legacy support: applies only to the ISP1563 

Legacy signals, IRQ1, IRQ12, A20OUT, KBIRQ1, MUIRQ12 and SMI#, are not normally 
used on a PCI add-on card design. In this case, the MUIRQ12 and KBIRQ1 input signals 
must be connected to GND. The other signals that are mentioned in this category (that 
are outputs) can be left open. 

Details on legacy signals and a block diagram showing correct connection of these 
signals in the case of onboard design can be found in 

ISP1563 Eval Board User Manual 

(UM10066). 

3.6 Overcurrent 

protection 

The ISP1562/3 implements the digital overcurrent protection scheme. 

The recommended solution to implement an external overcurrent protection is a standard 
power switch with integrated overcurrent detection, such as: 

• 

LM3526 and MIC2526 (2 ports), or 

• 

LM3544 (4 ports). 

The overcurrent protection logic of the ISP1562/3 uses the following two pins for each 
USB port: 

• 

PWEn_N: It is used to enable or disable the respective external port power switch. 
For example, MIC2526 and LM3526. 

• 

OCn_N: It is an input on which a fault condition on the respective USB port is 
signaled to the ISP1562/3 by the external port power-switching device. 

The fault condition that is usually signaled by an external power-switching device can be 
an overcurrent or a thermal shutdown. The port power-switching integrated devices 
commonly implement a delay of 1 ms to 3 ms to prevent false OC_N reporting because 
of inrush currents, when plugging a USB device. 

Once a fault condition is received, it will be detected by the operating system and the 
respective device driver will disable the port power switch by programming the Port 
Power (PP) bit in the PORTSC register. This device driver is the OHCI driver in the case 
of an Original USB device to create the fault condition, or the EHCI driver in the case of a 
Hi-Speed USB device to create the overcurrent condition. This is according to the USB 
port allocation at the moment when the OC# signal was asserted. 

A possible alternative is to use a resettable fuse on each port. This has the advantage of 
simplicity. It, however, does not inform the operating system of the fault condition and, 
therefore, no message is generated to inform the user. The resettable fuse will continue 
to protect the port by switching ‘on or off’ as long as the overcurrent condition persists. 

A possible enhancement of this scheme is connecting V

BUS

 to the OCn_N input of the 

ISP1562/3 to detect the OCn_N condition, the first time V

BUS

 is cut-off a LOW level will 

appear on the OCn_N pin. 

Using only an external PMOS transistor for overcurrent protection is not possible 
because the ISP1562/3 does not implement the analog overcurrent protection (not 
measuring the current through the transistor). 

Summary of Contents for ISP1562

Page 1: ...SP1563 Rev 04 1 November 2007 Application note Document information Info Content Keywords isp1562 isp1563 usb universal serial bus host pci adapter Abstract This document contains a description of the...

Page 2: ...or additional information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Revision history Rev Date Description 04 20071101 Fourth revision Corr...

Page 3: ...t controller device driver interacts with these registers to implement the USB functionality and the legacy support A detailed description of configuration registers and operational registers can be f...

Page 4: ...ct the presence of PCI VAUX 3 3 V and automatic selection of the input voltage Selection of PCI VCC 3 3 V must be the default position of jumper JP1 in the case of a standard add on card design The ot...

Page 5: ...ference EMI results A 48 MHz oscillator this may be a useful alternative typically in the case of on motherboard design Both solutions for the input clock are shown in the schematics To use a 48 MHz c...

Page 6: ...ve USB port is signaled to the ISP1562 3 by the external port power switching device The fault condition that is usually signaled by an external power switching device can be an overcurrent or a therm...

Page 7: ...he clearance imposed by the manufacturing process around any via holes to an internal plane Try to keep the length of the DP and DM traces equal The maximum trace length mismatch between high speed US...

Page 8: ...as possible to the USB connector Special attention must be given when placing additional components on the DP and DM lines and routing recommendations must be followed Both VDDA_AUX analog and VCC I...

Page 9: ...NNECTOR AD 31 0 PCICLK RST IDSEL GNT C BE0 C BE1 C BE2 C BE3 INTA REQ FRAME TRDY IRDY DEVSEL STOP PERR SERR PAR PME AD 31 0 PCICLK RST IDSEL GNT C BE0 C BE1 C BE2 C BE3 INTA REQ FRAME TRDY IRDY DEVSEL...

Page 10: ...23 AD 24 AD 25 AD 26 AD 27 AD 28 AD 29 AD 30 AD 31 AD0 AD1 AD2 AD4 AD3 70 69 68 67 66 65 AD5 AD6 63 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD2...

Page 11: ...5 12 V TCK GND TDO 5 V 5 V INTB INTD PRSNT 1 RESERVED PRSNT2 TRST 12 V TMS TDI 5 V INTA INTC 5 V RESERVED VIO RESERVED B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B...

Page 12: ...V Optional J1 1 2 3 5 VBUS C5 47 F 10 V C7 0 1 F C6 100 pF 5 6 7 8 R20 560 LED D2 C1 0 01 F C2 47 F 10 V C3 1 nF C4 22 F 10 V C41 0 1 F 5 VBUS FB8 BLM41PG600SN1 D1 LED 5V_Standby A TT1 TT2 B 5 V C42 0...

Page 13: ...E2 C BE3 INTA REQ FRAME TRDY IRDY DEVSEL STOP PERR SERR PAR PME PWE3 PWE4 DM1 DM2 DP2 ISP1563_ES1 ISP1563_ES1 SCH POWER_SWITCH POWER_SWITCH SCH RST GNT AD 31 0 PCICLK IDSEL C BE0 C BE1 C BE2 C BE3 INT...

Page 14: ...C BE 2 C BE 3 PCICLK IDSEL GNT AMB1 INTA REQ FRAME TRDY IRDY DEVSEL STOP PERR SERR PAR PME RST CLKRUN AMB2 AMB3 AMB4 GRN1 GRN2 GRN3 GRN4 OC1_N OC2_N OC3_N OC4_N PWE1_N PWE2_N PWE3_N PWE4_N DM1 DM2 DM...

Page 15: ...2 V TCK GND TDO 5 V 5 V INTB INTD PRSNT 1 RESERVED PRSNT2 TRST 12 V TMS TDI 5 V INTA INTC 5 V RESERVED VIO RESERVED B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34...

Page 16: ...USB1 IP 4220CZ6 1 2 3 4 6 5 ESD1 DM1 DM1 DP1 DP2 R17 15 k R18 15 k DP1 C7 0 1 F C56 220 F 10 V C44 1 nF FB3 BLM18PG121SN1 VBUS GND SHIELD SHIELD D D CON2 USB2 1 4 6 2 3 5 1 2 3 4 5 6 IP 4220CZ6 ESD2 R...

Page 17: ...in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publica...

Page 18: ...se 1 November 2007 Document identifier AN10050_4 7 Contents 1 Introduction 3 2 ISP1562 3 initialization 3 3 Description of the application schematics 4 3 1 Distribution of power sources and power mana...

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