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NXP Semiconductors 

AN10050

 

Designing a Hi-Speed USB host PCI adapter using ISP1562/63

AN10050_4 

© NXP B.V.  2007. All rights reserved.

Application note 

Rev. 04 — 1 November 2007 

7 of 18

4.  PCB design recommendations 

Some important recommendations for a successful PCB design, applicable to both 
adapter card and motherboard design solutions, are as follows: 

• 

Typically, a solution using four layers PCB (signal 1, GND, V

CC

, signal 2) is sufficient 

for proper routing, allowing you to obtain good functionality and meeting all 
compliance tests requirements. Start your design by placing the ISP1562/3 chip, the 
major components, and routing of the high-speed DP and DM traces and clock 
traces. Also, a complete ‘clean’ solution for routing the power and GND (split planes) 
must be defined before you start routing the rest of the signals. 

• 

The trace length for all PCI signals, except the PCI clock signal, to the PCI connector 
must be limited to a maximum of 1.5 inches. 

• 

The length of the PCI clock signal from the PCI bus connector to the ISP1562/3 must 
be 2.5 inches ± 0.1 inch in length and must be routed to only one load. It must 
usually be ‘snaked’. Ensure that all corners of this trace are rounded. Do not use 90

°

 

sharp corners. 

• 

Route the high-speed USB differential pairs over continuous GND or power planes. 
Avoid crossing anti-etch areas and any breaks in the internal planes (plane splits). 
The minimum recommended distance to a plane split is 25 mils. You must also avoid 
placing a series of via holes near the DP and DM lines because these will create 
‘break areas’ in the GND plane below. This is because of the clearance imposed by 
the manufacturing process around any via holes to an internal plane. 

• 

Try to keep the length of the DP and DM traces equal. The maximum trace length 
mismatch between high-speed USB signal pairs must not be greater than 70 mils. 

• 

Maintain parallelism between USB differential signals, with the trace spacing needed 
to achieve 90 

Ω

 differential impedance. To achieve the required impedance of the 

pair traces, it is recommended that you use 8 mils traces and keep the distance 
between the DP and DM traces at 8 mils. These values may vary, depending on the 
actual PCB parameters. 

• 

Avoid corners when routing the differential pairs DP and DM. Any 90

°

 direction 

change of traces must be accomplished with two 45

°

 turns or by using an arc of an 

imaginary circle tangent to the DP and DM lines. 

• 

Avoid routing the USB differential pairs near I/O connectors, signal headers, crystals, 
oscillators, magnetic devices and power connectors. 

• 

Maintain the maximum possible distance between high-speed USB differential pairs, 
high-speed or low-speed clock, and non-periodic signals. The minimum 
recommended distances are as follows: 

− 

20 mils between the DP and DM traces and low-speed non-periodic signal traces 

− 

50 mils between the DP and DM traces, and clock or high-speed periodic signal 
traces 

− 

20 mils between two pairs of the DP and DM traces 

• 

Avoid creating stubs to connect the 15 k

Ω

 pull-down resistors or to test points. If a 

stub is unavoidable in the design, no stub must be greater than 80 mils. 

• 

Route all the DP and DM lines on one layer. Do not change layers (avoid using vias) 
even to avoid crossing a plane split. It is better to place a non-split plane under high-
speed USB signals, ground layer or power layer. It is recommended that you place a 
ground layer beneath the DP and DM lines. 

Summary of Contents for ISP1562

Page 1: ...SP1563 Rev 04 1 November 2007 Application note Document information Info Content Keywords isp1562 isp1563 usb universal serial bus host pci adapter Abstract This document contains a description of the...

Page 2: ...or additional information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Revision history Rev Date Description 04 20071101 Fourth revision Corr...

Page 3: ...t controller device driver interacts with these registers to implement the USB functionality and the legacy support A detailed description of configuration registers and operational registers can be f...

Page 4: ...ct the presence of PCI VAUX 3 3 V and automatic selection of the input voltage Selection of PCI VCC 3 3 V must be the default position of jumper JP1 in the case of a standard add on card design The ot...

Page 5: ...ference EMI results A 48 MHz oscillator this may be a useful alternative typically in the case of on motherboard design Both solutions for the input clock are shown in the schematics To use a 48 MHz c...

Page 6: ...ve USB port is signaled to the ISP1562 3 by the external port power switching device The fault condition that is usually signaled by an external power switching device can be an overcurrent or a therm...

Page 7: ...he clearance imposed by the manufacturing process around any via holes to an internal plane Try to keep the length of the DP and DM traces equal The maximum trace length mismatch between high speed US...

Page 8: ...as possible to the USB connector Special attention must be given when placing additional components on the DP and DM lines and routing recommendations must be followed Both VDDA_AUX analog and VCC I...

Page 9: ...NNECTOR AD 31 0 PCICLK RST IDSEL GNT C BE0 C BE1 C BE2 C BE3 INTA REQ FRAME TRDY IRDY DEVSEL STOP PERR SERR PAR PME AD 31 0 PCICLK RST IDSEL GNT C BE0 C BE1 C BE2 C BE3 INTA REQ FRAME TRDY IRDY DEVSEL...

Page 10: ...23 AD 24 AD 25 AD 26 AD 27 AD 28 AD 29 AD 30 AD 31 AD0 AD1 AD2 AD4 AD3 70 69 68 67 66 65 AD5 AD6 63 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD2...

Page 11: ...5 12 V TCK GND TDO 5 V 5 V INTB INTD PRSNT 1 RESERVED PRSNT2 TRST 12 V TMS TDI 5 V INTA INTC 5 V RESERVED VIO RESERVED B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B...

Page 12: ...V Optional J1 1 2 3 5 VBUS C5 47 F 10 V C7 0 1 F C6 100 pF 5 6 7 8 R20 560 LED D2 C1 0 01 F C2 47 F 10 V C3 1 nF C4 22 F 10 V C41 0 1 F 5 VBUS FB8 BLM41PG600SN1 D1 LED 5V_Standby A TT1 TT2 B 5 V C42 0...

Page 13: ...E2 C BE3 INTA REQ FRAME TRDY IRDY DEVSEL STOP PERR SERR PAR PME PWE3 PWE4 DM1 DM2 DP2 ISP1563_ES1 ISP1563_ES1 SCH POWER_SWITCH POWER_SWITCH SCH RST GNT AD 31 0 PCICLK IDSEL C BE0 C BE1 C BE2 C BE3 INT...

Page 14: ...C BE 2 C BE 3 PCICLK IDSEL GNT AMB1 INTA REQ FRAME TRDY IRDY DEVSEL STOP PERR SERR PAR PME RST CLKRUN AMB2 AMB3 AMB4 GRN1 GRN2 GRN3 GRN4 OC1_N OC2_N OC3_N OC4_N PWE1_N PWE2_N PWE3_N PWE4_N DM1 DM2 DM...

Page 15: ...2 V TCK GND TDO 5 V 5 V INTB INTD PRSNT 1 RESERVED PRSNT2 TRST 12 V TMS TDI 5 V INTA INTC 5 V RESERVED VIO RESERVED B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34...

Page 16: ...USB1 IP 4220CZ6 1 2 3 4 6 5 ESD1 DM1 DM1 DP1 DP2 R17 15 k R18 15 k DP1 C7 0 1 F C56 220 F 10 V C44 1 nF FB3 BLM18PG121SN1 VBUS GND SHIELD SHIELD D D CON2 USB2 1 4 6 2 3 5 1 2 3 4 5 6 IP 4220CZ6 ESD2 R...

Page 17: ...in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publica...

Page 18: ...se 1 November 2007 Document identifier AN10050_4 7 Contents 1 Introduction 3 2 ISP1562 3 initialization 3 3 Description of the application schematics 4 3 1 Distribution of power sources and power mana...

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