NXP Semiconductors
UM11587
KITVR5510xA0EVM Evaluation Kit User Guideline
4.3.3 Jumpers
shows the location of jumpers on the KITVR5510xA0EVM board.
describes the jumper functions and settings.
Figure 3. Jumpers
Jumper
Function
Position
Description
1 – 2 shorted
VPRE
3 – 4 shorted
LDO1
5 – 6 shorted
LDO2
7 – 8 shorted
BUCK3
J8
VDDIO selection
9 – 10 shorted
(default)
VDDIO external LDO (supplied from FRDM- K82F board )
1 – 2 shorted
5 V to debug mode
J11
Debug mode selection 2 – 3 shorted
(default)
GND to normal mode
1 – 2 shorted
7P5V generated from VBAT/VIN directly
J12
Debug mode selection 2 – 3 shorted
(default)
7P5V generated from an onboard regulator
1 – 2 shorted
PWRON2 pin controlled by FRDM-K82F board
2 – 3 shorted
(default)
PWRON2 pin to GND
J13
PWRON2 I/O control
open
PWRON2 pin user controlled
1 – 2 shorted
PSYNC pin pulled up to VBOS
2 – 3 shorted
(default)
PSYNC pin to GND
J14
PSYNC I/O control
open
PSYNC controlled by FRDM-K82F board
Table 2. Jumpers
UM11587
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User manual
Rev. 1 — 3 May 2021
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