Monitor Initialization Code
C-40
M68VZ328ADS USER’S MANUAL
MOTOROLA
; Port D Registers
PDDIR
.equ
(M$418); Direction Reg
PDDATA
.equ
(M$419); Data Reg
PDPUEN
.equ
(M$41A); Pullup Enable Reg
PDSEL
.equ
(M$41B); Select Reg
PDPOL
.equ
(M$41C); Polarity Reg
PDIRQEN
.equ
(M$41D); IRQ Enable Reg
PDIRQEDGE .equ(M$41F); IRQ Edge Reg
; Port E Registers
PEDIR
.equ
(M$420); Direction Reg
PEDATA
.equ
(M$421); Data Reg
PEPUEN
.equ
(M$422); Pullup Enable Reg
PESEL
.equ
(M$423); Select Reg
; Port F Registers
PFDIR
.equ
(M$428); Direction Reg
PFDATA
.equ
(M$429); Data Reg
PFPUEN
.equ
(M$42A); Pullup Enable Reg
PFSEL
.equ
(M$42B); Select Reg
; Port G Registers
PGDIR
.equ
(M$430) ; Direction Reg
PGDATA
.equ
(M$431) ; Data Reg
PGPUEN
.equ
(M$432) ; Pullup Enable Reg
PGSEL
.equ
(M$433) ; Select Reg
PKSEL
.equ
(M$443) ; Select Reg
PMSEL
.equ
(M$44B) ; Select Reg
; PWM Registers
PWMC
.equ
(M$500); Control Reg
PWMS
.equ
(M$502); Sample Reg
PWMCNT
.equ
(M$504); Counter
; Timer Registers
; Timer 1 Registers
TCTL1
.equ
(M$600); Control Reg
TPRER1
.equ
(M$602); Prescalar Reg
TCMP1
.equ
(M$604); Compare Reg
TCR1
.equ
(M$606); Capture Reg
TCN1
.equ
(M$608); Counter
TSTAT1
.equ
(M$60A); Status Reg
; Watchdog Registers
WCR
.equ
(M$B0A); Control Reg
; SPI Registers
; SPI Master Registers
SPIMDATA
.equ(M$800); Control/Status Reg
SPIMCONT
.equ(M$802); Data Reg
; UART Registers
USTCNT
.equ
(M$900); Status Control Reg
UBAUD
.equ
(M$902); Baud Control Reg
UARTRX
.equ
(M$904); Rx Reg
UARTTX
.equ
(M$906); Tx Reg
UARTMISC
.equ(M$908); Misc Reg
UARTNIPR
.equ(M$90A) ; Non-Integer Prescalar Reg
; LCDC Registers
LSSA
.equ
(M$A00); Screen Start Addr Reg
LVPW
.equ
(M$A05); Virtual Page Width Reg
LXMAX
.equ
(M$A08); Screen Width Reg
LYMAX
.equ
(M$A0A); Screen Height Reg
LCXP
.equ
(M$A18); Cursor X Position
LCYP
.equ
(M$A1A); Cursor Y Position
LCWCH
.equ
(M$A1C); Cursor Width & Height Reg
LBLKC
.equ
(M$A1F); Blink Control Reg
LPICF
.equ
(M$A20); Panel Interface Config Reg
LPOLCF
.equ
(M$A21); Polarity Config Reg
LACDRC
.equ
(M$A23); ACD (M) Rate Control Reg
LPXCD
.equ
(M$A25); Pixel Clock Divider Reg
LCKCON
.equ
(M$A27); Clocking Control Reg
LRRA
.equ
(M$A29); Last Buffer Addr Reg
LOTCR
.equ
(M$A2B); Octet Terminal Count Reg
LPOSR
.equ
(M$A2D); Panning Offset Reg
LFRCM
.equ
(M$A31); Frame Rate Control Mod Reg
LGPMR
.equ
(M$A32); Gray Palette Mapping Reg
LIRQR
.equ
(M$A34); Interrupt Control Reg
; RTC Registers
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc.
..
