Synchronous DRAM Controller Module
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
7-3
Commands are issued to memory using specific encoding on address and control pins. After system reset,
a command must be sent to the SDRAM mode register to configure SDRAM operating parameters.
NOTE
Synchronous operation is selected by setting DCR[SO], DRAM controller
registers reflect the synchronous operation.
7.2.1
DRAM Controller Signals in Synchronous Mode
shows the behavior of DRAM signals in synchronous mode.
shows a typical signal configuration for synchronous mode.
Figure 7-2. MCF5253 SDRAM Interface
7.3
SDRAM Memory Map and Register Definitions
The memory map is shown in
. Field and bit descriptions are shown in the following sections.
Table 7-2. Synchronous DRAM Signal Connections
Signal
Description
SDRAS
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the
SDRAM. SDRAS should be connected to the corresponding SDRAM SRAS.
SDCAS
Synchronous column address strobe. Indicates a valid column address is present and can be latched by the
SDRAM. SDCAS should be connected to the corresponding signal labeled SCAS on the SDRAM.
SDWE
DRAM read/write. Asserted for write operations and negated for read operations.
SD_CS0
Chip Select for the SDRAM memory block connected to the MCF5253.
BCLKE
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs. Enables and
disables the clock internal to SDRAM. When BCLKE is low, memory can enter a power-down mode where
operations are suspended or they can enter self-refresh mode. BCLKE functionality is controlled by DCR[COC].
For designs using external multiplexing, setting COC allows BCLKE to provide command-bit functionality.
UDQM
LDQM
Column address strobe. For synchronous operation, UDQM, LDQM function as byte enables to the SDRAMs.
They connect to the DQM signals (or mask qualifiers) of the SDRAMs.
BCLK
Bus clock output. Connects to the CLK input of SDRAMs.
BCLK
A[31:0]
U/L DQM
SDWE
SDCAS
SDRAS
BCLKE
CKE
CAS
RAS
DQM
WE
ADDRESS
DATA
CLK
MCF5253
D[31:16]
SDRAM
CS
SD_CS0
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
