Synchronous DRAM Controller Module
MCF5253 Reference Manual, Rev. 1
7-4
Freescale Semiconductor
7.3.1
DRAM Controller Registers
The DRAM controller registers memory map is shown in
.
.
7.3.1.1
DRAM Control Register (DCR) (Synchronous Mode)
The DRAM control register (DCR),
, controls refresh logic.
Table 7-3. DRAM Controller Registers
MBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x100
Section 7.3.1, “DRAM Controller Registers”
]
Reserved
0x104
Reserved
0x108
DRAM address and control register 0 (DACR0) [See
Section 7.3.1.2, “DRAM Address and Control (DACR0)
]
0x10C
DRAM mask register block 0 (DMR0) [See
Section 7.3.1.3, “DRAM Controller Mask Registers (DMR0)”
]
0x110
Reserved
0x114
Reserved
Address MBAR + 0x100
Access: User read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
SO
NAM
COC
IS
RTIM
RC
W
Reset
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Figure 7-3. DRAM Control Register (DCR) (Synchronous Mode)
Table 7-4. DRAM Control Register (DCR) Field Descriptions (Synchronous Mode)
Field
Description
15
SO
Synchronous operation. Selects synchronous or asynchronous mode. When in synchronous mode, the DRAM
controller can be switched to ADRAM mode only by resetting the MCF5253.
0
Asynchronous DRAM. Default at reset. Do not use.
1
Synchronous DRAM
Note: bit setting SO = 0 is a legacy mode. Do not use. First action must always be to set this bit.
14
Reserved, should be cleared.
13
NAM
No address multiplexing. Some implementations require external multiplexing. For example, when linear addressing
is required, the DRAM should not multiplex addresses on DRAM accesses.
0
The DRAM controller multiplexes the external address bus to provide column addresses.
1
The DRAM controller does not multiplex the external address bus to provide column addresses.
12
COC
Command on SDRAM clock enable (BCLKE). Implementations that use external multiplexing (NAM = 1) must
support command information to be multiplexed onto the SDRAM address bus.
0
BCLKE functions as a clock enable; self-refresh is initiated by the DRAM controller through DCR[IS].
1
BCLKE drives command information. Because BCLKE is not a clock enable, self-refresh cannot be used (setting
DCR[IS]). Thus, external logic must be used if this functionality is desired. External multiplexing is also responsible
for putting the command information on the proper address bit.
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
