Bus Operation
MCF5253 Reference Manual, Rev. 1
8-8
Freescale Semiconductor
8.5.3
Write Cycle
The Write cycle as shown in
, will occur if the wait cycle field (WS) in the Chip Select Control
Register (CSR) is programmed to value “0000”. The CS low time is increased with
n
clocks if
n
is
programmed into the WS field.
During a write cycle, the MCF5253 sends data to the memory or to a peripheral device.
Figure 8-5. Write Cycle Flowchart
STATE 3
Data is made available by the external device and is sampled on the rising edge of BCLK with TA asserted. If TA
not asserted before the rising edge of BCLK at the end of the first clock cycle, the MCF5253 inserts wait states
(full clock cycles) until TA is asserted. If internal TA is requested (auto-acknowledge enabled in the chip select
control register, CSCR) then TA is generated internally by the chip select module.
STATE 4
During state 4, TA should be negated by the external device or if auto-acknowledge is enabled will be negated
internally by the chip select module.
STATE 5
CS and OE are negated on the falling edge of state 5 (S5). The MCF5253 stops driving the address lines and RW
on the rising edge of BCLK, terminating the read cycle. The external device must have its drive from the bus. The
external device must stop driving the bus.
The rising edge of BCLK may be the start of state 0 for the next access cycle.
1
The external device has a maximum of 1.5 BCLK cycles after the start of S4 to three-state the data bus after data is sampled
in S3 during a read cycle. This applies to basic read cycles and the last transfer of a burst.
2
The MCF5253 would not drive out data for a minimum of two BCLK cycles. However, another slave device may start driving
the bus as soon as its chip select is asserted. Chip select may be asserted at the beginning of S1, so bus drive must stop
before the end of S0. Under these conditions, data contention on the bus would not exist.
Table 8-6. Read Cycle States (continued)
State
Name
Description
1,2
1. Set RW to Write
2. Place Address on A[23:1]
3. Drive Data on D[31:16]
1. Decode Address
2. Store Data on D[31:16]
3. CS unit asserts TA (internal termination) or assert TA
externally for 1 BCLK cycle
(external termination).
1. Sample TA Low
2. Tri-State Data on D[31:16]
3. Start Next Cycle
External Memory/Device
MCF5253
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
