UART Modules
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
15-13
programming bit 2 of UMR1. UMR1 should also be programmed before enabling the transmitter and
loading the corresponding data bits into the transmit buffer.
In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it
is enabled or disabled. If the receiver is disabled, it sets the RxRDY bit and loads the character into the
receiver holding register FIFO, provided the received A/D bit is a one (address tag). The character is
discarded if the received A/D bit is a zero (data tag). If the receiver is enabled, all received characters are
transferred to the CPU using the receiver holding register stack during read operations.
In either case, the data bits are loaded into the data portion of the stack while the A/D bit is loaded into the
status portion of the stack normally used for a parity error (USR bit 5). Framing error, overrun error, and
break detection operate normally. The A/D bit takes the place of the parity bit; therefore, parity is neither
calculated nor checked. Messages in this mode can still contain error detection and correction information.
One way to provide error detection, if 8-bit characters are not required, is to use software to calculate parity
and append it to the 5-, 6-, or 7-bit character.
15.3.5
Bus Operation
This section describes the operation of the bus during read, write, and interrupt- acknowledge cycles to the
UART module. All UART module registers must be accessed as bytes.
15.3.5.1
Read Cycles
The CPU accesses the UART module with 1 to 2 wait states because the core system clock is divided by
2 for the UART module. The UART module responds to reads with byte data on D[7:0]. Reserved registers
return logic zero during reads.
15.3.5.2
Write Cycles
The CPU with zero wait states accesses the UART module. The UART module accepts write data on
D[7:0]. Write cycles to read-only registers and reserved registers complete in a normal manner without
exception processing; however, the data is ignored.
15.3.5.3
Interrupt Acknowledge Cycles
The UART module can arbitrate for interrupt servicing and supply the interrupt vector when it has
successfully won arbitration. The vector number must be provided if interrupt servicing is necessary; thus,
the interrupt vector register (UIVR) must be initialized.
The interrupt vector number generated by the IVR
is used if the autovector is not enabled in the SIM Interrupt Control Register (ICR). If the UIVR is not
initialized and the ICR is not programmed for autovector, a spurious interrupt exception is taken if
interrupts are generated. This works in conjunction with the MCF5253 interrupt controller, which allows
a programmable Interrupt Priority Level (IPL) for the interrupt.
15.4
UART Memory Map and Register Definitions
This section contains a detailed description of each register and its specific function as well as flowcharts
of basic UART module programming.
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
