Queued Serial Peripheral Interface (QSPI) Module
MCF5253 Reference Manual, Rev. 1
16-8
Freescale Semiconductor
In wraparound mode, the QSPI cycles through the queue continuously, even while requesting interrupt
service. QDLYR[SPE] is not cleared when the last command in the queue is executed. New receive data
overwrites previously received data in the receive RAM. Each time the end of the queue is reached,
QIR[SPIFE] is set. QIR[SPIF] is not automatically reset. If interrupt driven QSPI service is used, the
service routine must clear QIR[SPIF] to abort the current request. Additional interrupt requests during
servicing can be prevented by clearing QIR[SPIFE].
There are two recommended methods of exiting wraparound mode: clearing QWR[WREN] or setting
QWR[HALT]. Exiting wraparound mode by clearing QDLYR[SPE] is not recommended because this may
abort a serial transfer in progress. The QSPI sets SPIF, clears QDLYR[SPE], and stops the first time it
reaches the end of the queue after QWR[WREN] is cleared. After QWR[HALT] is set, the QSPI finishes
the current transfer, then stops executing commands. After the QSPI stops, QDLYR[SPE] can be cleared.
16.4
QSPI Memory Map and Register Definitions
The programming model for the QSPI consists of six registers. They are the QSPI mode register (QMR),
QSPI delay register (QDLYR), QSPI wrap register (QWR), QSPI interrupt register (QIR), QSPI address
register (QAR), and the QSPI data register (QDR).
There are a total of 80 bytes of memory used for transmit, receive, and control data. This memory is
accessed indirectly using QAR and QDR.
Registers and RAM are written and read by the CPU.
16.4.1
QSPI Mode Register (QMR)
The QMR register, shown in
, determines the basic operating modes of the QSPI module.
Parameters such as clock polarity and phase, baud rate, master mode operation, and transfer size are
determined by this register. The data output high impedance enable, DOHIE, controls the operation of
QSPI_Dout between data transfers. When DOHIE is cleared, QSPI_Dout is actively driven between
transfers. When DOHIE is set, QSPI_Dout assumes a high impedance state.
NOTE
Because the QSPI does not operate in slave mode, the master mode enable
bit, QMR[MSTR], must be set for the QSPI module to operate correctly.
Address MBAR + 0x400
Access: User read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
MSTR DOHIE
BITS
CPOL CPHA
BAUD
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
Figure 16-3. QSPI Mode Register (QMR)
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
