IEEE 1149.1 Test Access Port (JTAG)
MCF5253 Reference Manual, Rev. 1
21-4
Freescale Semiconductor
instruction operations occur. TMS has an internal pullup so that if it is not driven low, its value will default
to a logic level of 1. However, if TMS will not be used, it should be tied to Vdd. This pin also signals a
hardware breakpoint to the processor when in the debug mode.
21.3.4
Test Data Input/Development Serial Input (TDI/DSI)
This is a dual-function pin. If TEST[2:0] = 001, then DSI is selected. If TEST[2:0] = 000, then TDI is
selected. When used as TDI, this input signal provides the serial data port for loading the various JTAG
shift registers composed of the boundary scan register, the bypass register, and the instruction register.
Shifting in of data depends on the state of the JTAG controller state machine and the instruction currently
in the instruction register. This data shift occurs on the rising edge of TCK. TDI also has an internal pullup
so that if it is not driven low its value will default to a logic level of 1. However, if TDI will not be used,
it should be tied to VDD.
This pin also provides the single-bit communication for the debug module commands.
21.3.5
Test Data Output/Development Serial Output (TDO/DSO)
This is a dual-function pin. When TEST[2:0] = 001, then DSO is selected. When TEST[2:0] = 000, TDO
is selected. When used as TDO, this output signal provides the serial data port for outputting data from the
JTAG logic. Shifting out of data depends on the state of the JTAG controller state machine and the
instruction currently in the instruction register. This data shift occurs on the falling edge of TCK. When
TDO is not outputting test data, it is tri-stated. TDO can also be placed in tri-state mode to allow bussed
or parallel connections to other devices having JTAG.
21.4
TAP Controller
The state of TMS at the rising edge of TCK determines the current state of the TAP controller. There are
basically two paths that the TAP controller can follow: The first, for executing JTAG instructions; the
second, for manipulating JTAG data based on the JTAG instructions. The various states of the TAP
controller are shown in
. For more detail on each state, refer to the IEEE 1149.1A Standard
JTAG document.
NOTE
From any state that the TAP controller is in, Test-Logic-Reset can be entered
if TMS is held high for at least five rising edges of TCK.
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
