Advanced Technology Attachment Controller (ATA)
MCF5253 Reference Manual, Rev. 1
23-2
Freescale Semiconductor
Figure 23-1. ATA Interface Block Diagram
23.3
Overview
The ATA block is a AT attachment host interface. Its main use is to interface with IDE hard disc drives and
ATAPI optical disc drives. It interfaces with the ATA device over a number of ATA signals.
The ATA interface is compliant to the ATA-6 standard and supports the following protocols:
•
PIO mode 0, 1, 2, 3, and 4
•
multiword DMA mode 0, 1, and 2
•
Ultra DMA modes 0, 1, 2, 3, and 4 with bus clock of 50 MHz or higher
The ATA interface has 2 busses connected:
•
One CPU bus for communication with the host processor
•
One DMA bus for communication with the host DMA unit
All internal registers are visible from both busses, allowing smart DMA access to program the interface.
Before accessing the ATA bus, the host must program the timing parameters to be used on the ATA bus.
The timing parameters control the timing on the ATA bus. Most timing parameters are programmable as a
number of clock cycles (1 to 255). Some are implied.
After programming the timing parameters, there are two protocols that can be active at the same time on
the ATA bus:
•
First protocol. This protocol is a PIO mode access that can be performed at any time by the host
CPU or the host smart DMA to the ATA bus. During PIO mode access, the incoming IP bus cycle
is translated to an ATA bus cycle by the ATA protocol engine. The IP bus cycle is stalled until
completion of the ATA bus cycle on read, or until putting the write data on the ATA bus on write.
FIFO
128 bytes
ATA_RST
ATA_DIOR
ATA_DIOw
ATA_CS1
ATA_CS0
ATA_A2
ATA_A1
ATA_A0
ATA_DMARQ
ATA_DMACK
ATA_INTRQ
ATA_IORDY
ATA_D[15:0]
ATA
Protocol
Engine
Timing
Parameters
Control
Register
Interrupt
Interface
FIFO
control
Bus
Interface
CPU
Bus
DMA
Bus
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
