Signal Description
MCF5253 Reference Manual, Rev. 1
2-6
Freescale Semiconductor
Bits 23 down to 1 and 24 of the address are available. A24 is intended to be used with 256 Mbit DRAM’s.
Signals are named:
•
A[23:1]
•
A20/24
2.3.2
Read-Write Control
This signal indicates during any bus cycle whether a read or write is in progress. A low is write cycle and
a high is a read cycle.
2.3.3
Output Enable
The OE signal is intended to be connected to the output enable of asynchronous memories connected to
chip selects. During bus read cycles, the ColdFire processor will drive OE low.
2.3.4
Data Bus
The data bus (D[31:16]) is bi-directional and non-multiplexed. Data is registered by the MCF5253 on the
rising clock edge. The data bus uses a default configuration if none of the chip-selects or DRAM bank
match the address decode. All 16 bits of the data bus are driven during writes, regardless of port width or
operand size.
2.3.5
Transfer Acknowledge
The TA/GPIO12 pin is the transfer acknowledge signal.
2.4
SDRAM Controller Signals
The following SDRAM signals provide a glueless interface to external SDRAM. An SDRAM width of 16
bits is supported and can access as much as 32MBs of memory. ADRAMs are not supported.
Table 2-2. SDRAM Controller Signals
SDRAM Signal
Description
Synchronous DRAM row address strobe The SDRAS/GPIO59 active low pin provides a seamless interface to the RAS input
on synchronous DRAM
Synchronous DRAM
column address strobe
The SDCAS/GPIO39 active low pin provides a seamless interface to CAS input on
synchronous DRAM.
Synchronous DRAM write
The SDWE/GPIO38 active-low pin is asserted to signify that a SDRAM write cycle is
underway. This pin outputs logic ‘1’ during read bus cycles.
Synchronous DRAM chip enable
The SD_CS0/GPIO60 active-low output signal is used during synchronous mode to
route directly to the chip select of a SDRAM device.
Synchronous DRAM UDQM and
LQDM signals
The DRAM byte enables UDMQ and LDQM are driven by the SDUDQM/GPO53 and
SDLDQM/GPO52 byte enable outputs.
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
