Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
24-60
Freescale Semiconductor
7–0
Status
This field is used by the host controller to communicate individual command execution states back to the
host controller driver (HCD) software. This field contains the status of the last transaction performed on
this qTD. The bit encodings are:
Bit
Status Field Description
7
Active. Set by the software to enable the execution of transactions by the host controller.
6
Halted. Set by the host controller during status updates to indicate that a serious error has
occurred at the device/endpoint addressed by this qTD. This can be caused by babble, the
error counter counting down to zero, or reception of the STALL handshake from the device
during a transaction. Any time that a transaction results in the Halted bit being set, the Active
bit is also cleared.
5
Data Buffer Error. Set by the host controller during status update to indicate that the host
controller is unable to keep up with the reception of incoming data (overrun) or is unable to
supply data fast enough during transmission (under run). If an overrun condition occurs, the
host controller will force a time-out condition on the USB, invalidating the transaction at the
source. If the host controller sets this bit to a one, then it remains a one for the duration of
the transfer.
4
Babble Detected. Set by the host controller during status update when babble is detected
during the transaction. In addition to setting this bit, the host controller also sets the Halted
bit to a one. Since babble is considered a fatal error for the transfer, setting the Halted bit to
a one insures that no more transactions occur because of this descriptor.
3
Transaction Error (XactErr). Set by the host controller during status update in the case
where the host did not receive a valid response from the device (time-out, CRC, bad PID).
If the host controller sets this bit to a one, then it remains a one for the duration of the
transfer.
2
Missed Micro-Frame. This bit is ignored unless the QH[EPS] field indicates a full- or
low-speed endpoint and the queue head is in the periodic list. This bit is set when the host
controller detected that a host-induced hold-off caused the host controller to miss a required
complete-split transaction. If the host controller sets this bit to a one, then it remains a one
for the duration of the transfer.
1
Split Transaction State (SplitXstate). This bit is ignored by the host controller unless the
QH[EPS] field indicates a full- or low-speed endpoint. When a full- or low-speed device, the
host controller uses this bit to track the state of the split- transaction. The functional
requirements of the host controller for managing this state bit and the split transaction
protocol depends on whether the endpoint is in the periodic or asynchronous schedule. The
bit encodings are:
0 Do Start Split. This value directs the host controller to issue a Start split transaction to
the endpoint.
1 Do Complete Split. This value directs the host controller to issue a Complete split
transaction to the endpoint.
0
Ping State (P)/ERR. If the QH[EPS] field indicates a high-speed device and the PID Code
indicates an OUT endpoint, then this is the state bit for the Ping protocol. The bit encodings
are:
0 Do OUT. This value directs the host controller to issue an OUT PID to the endpoint.
1 Do Ping. This value directs the host controller to issue a PING PID to the endpoint.
If the QH[EPS] field does not indicate a high-speed device, then this field is used as an error
indicator bit. It is set by the host controller whenever a periodic split-transaction receives an
ERR handshake.
Table 24-53. qTD Token (DWord 2) (continued)
Bit
Name
Description
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
