Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
24-118
Freescale Semiconductor
NOTE
The only method the software should use for acknowledging an interrupt is
by transitioning the appropriate status bits in the USBSTS register from a
one to a zero.
24.9.14.1 Transfer/Transaction Based Interrupts
These interrupt sources are associated with transfer and transaction progress. They are all dependent on
the next interrupt threshold.
24.9.14.1.1
Transaction Error
A transaction error is any error that caused the host controller to think that the transfer did not complete
successfully.
lists the events/responses that the host can observe as a result of a transaction.
The effects of the error counter and interrupt status are summarized in the following paragraphs. Most of
these errors set the XactErr status bit in the appropriate interface data structure.
There is a small set of protocol errors that relate only when executing a queue head and fit under the
umbrella of a WRONG PID error that are significant to explicitly identify. When these errors occur, the
XactErr status bit in the queue head is set and the Cerr field is decremented. When the PID Code indicates
a SETUP, the following responses are protocol errors and result in XactErr bit being set and the Cerr field
being decremented.
•
EPS field indicates a high-speed device and it returns a Nak handshake to a SETUP.
•
EPS field indicates a high-speed device and it returns a Nyet handshake to a SETUP.
•
EPS field indicates a low- or full-speed device and the complete-split receives a Nak handshake.
24.9.14.1.2
Serial Bus Babble
When a device transmits more data on the USB than the host controller is expecting for this transaction, it
is defined to be babbling. In general, this is called a Packet Babble. When a device sends more data than
the Maximum Length number of bytes, the host controller sets the Babble Detected bit to a one and halts
Table 24-72. Summary of Transaction Errors
Event/
Result
Queue Head/qTD/iTD/siTD Side Effects
USBSTS[USBERRINT]
Cerr
Status Field
CRC
-1
XactErr set
1
1
1
If occurs in a queue head, then USBERRINT is asserted only when Cerr counts down from a one to a
zero. In addition the queue is halted.
Timeout
-1
XactErr set
Bad PID
2
2
The host controller received a response from the device, but it could not recognize the PID as a valid PID.
-1
XactErr set
Babble
N/A
See
Section 24.9.14.1.2, “Serial Bus Babble”
1
Buffer Error
N/A
See
Section 24.9.14.1.3, “Data Buffer Error”
–
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
