Queued Serial Peripheral Interface (QSPI) Module
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
16-3
•
16 transmit data words (transfer RAM)
•
16 receive data words (transfer RAM)
RAM is organized so that 1 byte of command control data, 1 word of transmit data, and 1 word of receive
data comprise 1 queue entry.
The user initiates QSPI operation by loading a queue of commands in command RAM, writing transmit
data into transmit RAM, and then enabling the QSPI data transfer. The QSPI executes the queued
commands and sets the completion flag in the QSPI interrupt register (QIR[SPIF]) to signal their
completion. Optionally, QIR[SPIFE] can be enabled to generate an interrupt.
The QSPI uses four queue pointers. The user can access three of them through fields in QSPI Wrap
Register (QWR):
•
The new queue pointer, QWR[NEWQP], points to the first command in the queue.
•
An internal queue pointer points to the command currently being executed.
•
The completed queue pointer, QWR[CPTQP], points to the last command executed.
•
The end queue pointer, QWR[ENDQP], points to the final command in the queue.
The internal pointer is initialized to the same value as QWR[NEWQP]. During normal operation, the
following sequence repeats:
1. The command pointed to by the internal pointer is executed.
2. The value in the internal pointer is copied into QWR[CPTQP].
3. The internal pointer is incremented.
Execution continues at the internal pointer address unless the QWR[NEWQP] value is changed. After each
command is executed, QWR[ENDQP] and QWR[CPTQP] are compared. When a match occurs,
QIR[SPIF] is set and the QSPI stops unless wraparound mode is enabled. Setting QWR[WREN] enables
wraparound mode.
QWR[NEWQP] is cleared at reset. When the QSPI is enabled, execution begins at address 0x0 unless
another value has been written into QWR[NEWQP]. QWR[ENDQP] is cleared at reset but is changed to
show the last queue entry before the QSPI is enabled. QWR[NEWQP] and QWR[ENDQP] can be written
at any time. When the QWR[NEWQP] value changes, the internal pointer value also changes unless a
transfer is in progress, in which case the transfer completes normally. Leaving QWR[NEWQP] and
QWR[ENDQP] set to 0x0 causes a single transfer to occur when the QSPI is enabled.
Data is transferred relative to QSPI_CLK which can be generated in any one of four combinations of phase
and polarity using QMR[CPHA, CPOL]. Data is transferred most significant bit (msb) first. The number
of bits transferred defaults to eight, but can be set to any value from 8 to 16 by writing a value into the
BITSE field of the command RAM, QCR[BITSE].
16.3.1
QSPI RAM
The QSPI contains an 80-byte block of static RAM that can be accessed by both the user and the QSPI.
This RAM does not appear in the MCF5253 memory map because it can only be accessed by the user
indirectly through the QSPI address register (QAR) and the QSPI data register (QDR).
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
