Queued Serial Peripheral Interface (QSPI) Module
MCF5253 Reference Manual, Rev. 1
16-6
Freescale Semiconductor
Data transfer is synchronized with the internally generated QSPI_CLK, whose phase and polarity are
controlled by QMR[CPHA] and QMR[CPOL]. These control bits determine which QSPI_CLK edge is
used to drive outgoing data and to latch incoming data.
16.3.2
Baud Rate Selection
Baud rate is selected by writing a value from 2 to 255 into QMR[BAUD]. The QSPI uses a prescaler to
derive the QSPI_CLK rate from the system clock, SYSCLK, divided by two.
A baud rate value of zero turns off the QSPI_CLK.
The desired QSPI_CLK baud rate is related to SYSCLK and QMR[BAUD] by the following expression:
QMR[BAUD] = SYSCLK / [2
×
(desired QSPI_CLK baud rate)] (SYSCLK = CORE operating
frequency / 2).
16.3.3
Transfer Delays
The QSPI supports programmable delays for the QSPI_CS signals. The time between QSPI_CS assertion
and the leading QSPI_CLK edge, and the time between the end of one transfer and the beginning of the
next, are both independently programmable.
The chip select to clock delay enable (DSCK) bit in command RAM, QCR[DSCK], enables the
programmable delay period from QSPI_CS assertion until the leading edge of QSPI_CLK. QDLYR[QCD]
determines the period of delay before the leading edge of QSPI_CLK. The following expression
determines the actual delay before the QSPI_CLK leading edge:
QSPI_CS-to-QSPI_CLK delay = QCD/SYSCLK frequency
QCD has a range of 1 to 127
When QCD or DSCK equals zero, the standard delay of one-half the QSPI_CLK period is used.
The delay after transmit enable (DT) bit in command RAM enables the programmable delay period from
the negation of the QSPI_CS signals until the start of the next transfer. The delay after transfer can be used
to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to
allow serial A/D converters to complete conversion. There are two transfer delay options: the user can
Table 16-2. QSPI_CLK Frequency as Function of SYSCLK and Baud Rate
SYSCLK
QMR [BAUD]
70 MHz
48 MHz
33 MHz
20 MHz
2
17,500,000
12,000,000
8,250,000
5,000,000
4
8,750,000
6,000,000
4,125,000
2,500,000
8
4,375,000
3,000,000
2,062,500
1,250,000
16
2,187,500
1,500,000
1,031,250
625,000
32
1,093,750
750,000
515,625
312,500
255
546,875
94,118
64,706
39,216
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
