Queued Serial Peripheral Interface (QSPI) Module
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
16-11
16.4.4
QSPI Interrupt Register (QIR)
12
CSIV
QSPI_CS inactive level.
0 QSPI chip select outputs return to zero when not driven from the value in the current command RAM entry during
a transfer (that is, inactive state is 0, chip selects are active high).
1 QSPI chip select outputs return to one when not driven from the value in the current command RAM entry during
a transfer (that is, inactive state is 1, chip selects are active low).
11–8
ENDQP
End of queue pointer. Points to the RAM entry that contains the last transfer description in the queue.
7–4
CPTQP
Completed queue entry pointer. Points to the RAM entry that contains the last command to have been completed.
This field is read only.
3–0
NEWQP
Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a transfer.
Address MBAR + 0x40C
Access: User read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
WCEFB
ABRTB
ABRTL
WCEFE
ABRTE
SPIFE
WCEF
ABRT
SPIF
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-7. QSPI Interrupt Register (QIR)
Table 16-6. QSPI Interrupt Register (QIR) Field Descriptions
Field
Description
15
WCEFB
Write collision access error enable. A write collision occurs during a data transfer when the RAM entry containing the
command currently being executed is written to by the CPU with the QDR. When this bit is asserted, the write access
to QDR results in an access error.
14
ABRTB
Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a transfer. When set, an attempt to
clear QDLYR[SPE] during a transfer results in an access error.
13
Reserved, should be cleared.
12
ABRTL
Abort lock-out. When set, QDLYR[SPE] cannot be cleared by writing to the QDLYR. QDLYR[SPE] is only cleared by
the QSPI when a transfer completes.
11
WCEFE
Write collision interrupt enable. Interrupt enable for WCEF. Setting this bit enables the interrupt, and clearing it
disables the interrupt.
10
ABRTE
Abort interrupt enable. Interrupt enable for ABRT flag. Setting this bit enables the interrupt, and clearing it disables
the interrupt.
9
Reserved, should be cleared.
8
SPIFE
QSPI finished interrupt enable. Interrupt enable for SPIF. Setting this bit enables the interrupt, and clearing it disables
the interrupt.
7–4
Reserved, should be cleared.
Table 16-5. QSPI Wrap Register (QWR) Field Descriptions (continued)
Field
Description
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
