Audio Interface Module (AIM)
MCF5253 Reference Manual, Rev. 1
17-34
Freescale Semiconductor
17.7.7
Audio Interrupts
17.7.7.1
AudioTick Interrupts
The audio tick interrupt is an interrupt to sustain an interrupt routine that is synchronous with one of the
audio interfaces, but not directly related to any FIFO being full or empty. Two fields control how this
interrupt is generated:
1. The source field controls the source event.
2. The count field controls the number of events (sample pairs) between any two audioTick interrupts.
For example, if the source is set to IIS1 Tx FIFO / Read, and count is set to three, the interrupt will occur
after every three read strobes to the IIS1 Tx FIFO. Even if the FIFO is in reset state, the interrupt will
continue running.
17.7.7.2
PDIR1, PDIR2, and PDIR3, Interrupts
With FIFO’s feeding data to the PDIR registers, three interrupts are associated.
1. Full
2. Under/over
3. Resync
6
PDIR1 FIFO AUTO SYNC
0 Auto synchronization off
1 Auto synchronization on
0
5–3
AUDIO TICK COUNT
000 1 Interrupt for every event
001 2 Interrupt for every 2 events
010 3
011 4
100 5
Other Reserved, unused
000
11, 2–0 AUDIO TICK SOURCE
0 000 Off
0 001 IIS1 Tx Right FIFO / Read
0 010 IIS2 Tx Right FIFO / Read
0 011 EBU Tx Right FIFO / Read
0 100 IIS1 Rcv Data
0 101 IIS3 Rcv Data
0 110 Reserved
0 111 EBU1 Rcv Data
1 000 EBU2 Rcv Data
000
1
The automatic FIFO resynchronization can be switched on, and will avoid all mismatch between left and right
FIFO
‘s, if
the software obeys following rules:
1.When left data is read or written to the left FIFO, in the same place of the program, data must be read or written to the
right
FIFO
. Maximum time difference between left and right is 1/2 sample clock. (E.g. if the sample frequency is 44 kHz,
then this is approximately 10 micro-seconds. For 88 kHz, then this approximately 5 micro-seconds.)
2.Writing or reading data to the FIFO ‘s must be at least 2 samples at the time. If there is a mis-match between Left-Right,
the resync logic may go on only 1 sample clock after last data is read/written to the FIFO. Also acceptable is polling the
FIFO
, if at least part of the time, 2 samples will be read/written to it.
Table 17-19. audioGlob Register Field (0xCE) Descriptions (continued)
Field
Name
Description
1
Reset
Notes
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
