Advanced Technology Attachment Controller (ATA)
MCF5253 Reference Manual, Rev. 1
23-4
Freescale Semiconductor
It is the task of the host CPU or the host smart DMA unit to read data or write data to the FIFO to
keep the transfer going. Normal set-up is that the host (smart) DMA unit takes on this task. For this
purpose, the
fifo_rcv_alarm
and fifo_tx_alarm signals are sent to the host DMA unit.
fifo_rcv_alarm
informs the host DMA unit that there is at least 1 packet of data waiting in the FIFO
to be read by the host DMA. Whenever this signal is high, the host DMA should transfer one packet
of data from the FIFO to the main memory. Typical packet size is 32 bytes (8 long words), but other
packet sizes can be handled too.
fifo_tx_alarm
informs the host DMA unit that there is space for at
least 1 packet to be written by the host DMA. Whenever this signal is high, the host DMA should
transfer one packet of data from main memory to the FIFO. Typical packet size is 32 bytes (8 long
words), but other packet sizes can be handled too.
23.4
External Signal Description
for the list of signals entering and exiting this module to peripherals within the device.
23.4.1
Detailed Signal Descriptions
For a detailed description of the ATA bus signal, refer to the ATA-6 specification.
23.4.1.1
ATA_RST (Out)
This signal is the ATA reset signal. When low, the ATA bus is in reset state. When high, no reset. The ATA
bus is in reset whenever the appropriate bit in the control register is cleared. After system reset, the ATA
bus is in reset.
Table 23-1. Signal Properties
Name
Function
Reset State
Direction
ATA_RST
ATA bus reset signal. Active low. If active,
ata device is reset
1
1
This signal is a standard ATA bus signal. It conforms with the ATA specification.
0
O
ATA_DIOR
ATA bus read strobe
1
O
ATA_DIOW
ATA bus write strobe
1
O
ATA_CS1
ATA bus chip select 1
1
O
ATA_CS0
ATA bus chip select 0
1
O
ATA_A2
ATA bus address line 2
0
O
ATA_A1
ATA bus address line 1
0
O
ATA_A0
ATA bus address line 0
0
O
ATA_DMARQ
ATA bus DMA request
–
I
ATA_DMACK
ATA bus DMA acknowledge
1
O
ATA_INTRQ
ATA bus interrupt request
–
I
ATA_IORDY
ATA bus iordy
–
O
ATA_D[15:0]
ATA data bus (little-endian)
HI_Z
Tri-state I/O
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
