Advanced Technology Attachment Controller (ATA)
MCF5253 Reference Manual, Rev. 1
23-28
Freescale Semiconductor
23.5.2.5
Interrupt Registers
A group of three registers control the interrupt interface from the ATA module and going to the CPU and
DMA. There are two interrupts controlled by these registers:
Address MBAR2 + 0x824 (ATA_CONTROL)
Access: User read/write
7
6
5
4
3
2
1
0
R
fifo_rst_b
ata_rst_b
fifo_tx_en
fifo_rcv_en
dma_pending
dma_ultra_selected
dma_write
iordy_en
W
Reset
0
0
0
0
0
0
0
0
Figure 23-39. ATA_Control Register
Table 23-10. ATA Control Register Field Descriptions
Field
Description
7
fifo_rst_b
This field controls if the internal FIFO is in reset or enabled.
0 FIFO
reset
1 FIFO normal operation
6
ata_rst_b
This bit controls the level on the ata_reset_b pin, and controls the reset of the internal ata protocol engine.
0 ata_reset_b = 0, ata drive is reset, and internal protocol engine reset.
1 ata_reset_b = 1, ata drive is not reset and internal protocol engine normal operation.
5
fifo_tx_en
FIFO transmit enable. This bit controls if the FIFO will make transmit data requests to the DMA. If enabled,
the FIFO will request the DMA to refill it whenever FIFO filling drops below the alarm level.
0 FIFO refill by DMA disabled
1 FIFO refill by DMA enabled
4
fifo_rcv_en
FIFO receive enable. This bit controls if the FIFO will make receive data requests to the DMA. If enabled,
the FIFO will request the DMA to empty it whenever FIFO filling becomes greater or equal to the alarm
level.
0 FIFO empty by DMA disabled
1 FIFO empty by DMA enabled
3
dma_pending
DMA pending bit. This bit controls if the ATA interface will respond to a DMA request originating in the
drive. If this bit is asserted, the ATA interface will start a multiword DMA or ultra DMA burst whenever the
drive asserts ATA_DMARQ.
0 ATA interface will not start DMA burst
1 ATA interface will start multiword DMA or ultra DMA burst whenever drive asserts dmarq
2
dma_ultra_selected
This bit indicates if a DMA burst started, the UDMA or MDMA protocol will be used.
0 Multiword DMA protocol will be used
1 Ultra DMA protocol will be used
1
dma_write
This bit indicates the data direction on any DMA burst started.
0 DMA in burst, ATA interface reads from drive
1 DMA out burst, ATA interface writes to drive
0
iordy_en
This bit indicates if the ATA_IORDY handshake will be used during PIO mode.
0 IORDY will be disregarded
1 IORDY handshake will be used
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
