Advanced Technology Attachment Controller (ATA)
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
23-31
23.5.2.5.3
Interrupt_Clear Register
for illustration of valid bits in the Interrupt_Clear Register and
for
description of the bit fields.
23.5.2.6
FIFO Alarm Register
for illustration of valid bits in the FIFO_Alarm Register.
3
ata_intrq2
ATA interrupt request 2. This bit reflects the value of the ATA_INTRQ interrupt input. It is set in the interrupt
pending register when the drive interrupt is pending, cleared otherwise. It has exactly same functioning as
ata_intrq1, but this bit affects ipbus_int, while the other affects interrupt to the DMA. When the bit is set in the
interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be asserted,
signalling the CPU the drive is requesting attention. The interrupt clear register has no influence on this bit.
2–0
Uncommitted
N/A
Address MBAR2 + 0x830 (INTERRUPT_CLEAR)
Access: User write-only
7
6
5
4
3
2
1
0
R
W
fifo_underflow
fifo_overflow
Reset
–
–
–
–
–
–
–
–
Figure 23-42. Interrupt_Clear Register
Table 23-13. Interrupt Clear Register Field Description
Field
Description
7
Uncommitted
N/A
6
fifo_underflow
FIFO underfow. This bit reports FIFO underflow. Sticky bit. It is set in the interrupt pending register when there
is a FIFO underflow condition. It is cleared by writing a ‘1’ to this bit in the interrupt clear register. When the bit
is set in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be
active, signalling interrupt to the cpu.
5
fifo_overflow
FIFO overflow. This bit reports FIFO overflow. Sticky bit. It is set in the interrupt pending register when there is
a FIFO overflow condition. It is cleared by writing a ‘1’ to this bit in the interrupt clear register. When the bit is set
in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be active,
signalling interrupt to the cpu.
4–0
Uncommitted
N/A
Table 23-12. Interrupt Enable Register Field Description (continued)
Field
Description
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
