Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
24-40
Freescale Semiconductor
24.6.3.18 Endpoint Flush Register (ENDPTFLUSH), Non-EHCI
This register is not defined in the EHCI specification. This register is used by the USB OTG module only
in device mode.
Table 24-31. Endpoint Initialization (ENDPTPRIME) Register Field Descriptions
Field
Description
31–20
Reserved.
19–16
PETB
Prime endpoint transmit buffer. For each endpoint, a corresponding bit is used to request that a buffer prepared for a
transmit operation in order to respond to a USB IN/INTERRUPT transaction. The software should write a one to the
corresponding bit when posting a new transfer descriptor to an endpoint. The hardware will automatically use this bit
to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. The hardware will
clear this bit when the associated endpoint(s) is (are) successfully primed. PETB[3] (bit 19 of the register) corresponds
to endpoint 3.
Note: These bits will be momentarily set by the hardware during hardware re-priming operations when a dTD is
retired, and the dQH is updated.
15–4
Reserved.
3–0
PERB
Prime endpoint receive buffer. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive
operation in order to respond to a USB OUT transaction. The software should write a one to the corresponding bit
whenever posting a new transfer descriptor to an endpoint. The hardware will automatically use this bit to begin
parsing for a new transfer descriptor from the queue head and prepare a receive buffer. The hardware will clear this
bit when the associated endpoint(s) is (are) successfully primed.
Note: These bits will be momentarily set by the hardware during hardware re-priming operations when a dTD is
retired, and the dQH is updated.
Address MBAR2 + 0x7B4
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
FETB
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
FERB
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 24-30. Endpoint Flush (ENDPTFLUSH) Register
Table 24-32. Endpoint Flush (ENDPTFLUSH) Register Field Descriptions
Field
Description
31–20 Reserved.
19–16
FETB
Flush endpoint transmit buffer. Writing a one to a bit(s) in this register will cause the associated endpoint(s) to clear any
primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until
completion. The hardware will clear this register after the endpoint flush operation is successful.
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
