Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
24-65
The DWords 4–11 of a queue head are the transaction overlay area. This area has the same base structure
as a Queue Element Transfer Descriptor. The queue head utilizes the reserved fields of the page pointers
to implement tracking the state of split transactions.
This area is characterized as an overlay because when the queue is advanced to the next queue element,
the source queue element is merged onto this area. This area serves an execution cache for the transfer.
24.8.7
Periodic Frame Span Traversal Node (FSTN)
This data structure is to be used only for managing Full- and Low-speed transactions that span a
Host-frame boundary. The software must not use an FSTN in the Asynchronous Schedule. An FSTN in
the Asynchronous schedule results in undefined behavior. The software must not use the FSTN feature
with a host controller whose HCIVERSION register indicates a revision implementation below 0x0096.
Note that FSTNs were not defined for EHCI implementations before Revision 0.96 of the EHCI
Specification and their use may yield undefined results.
Table 24-59. Host-Controller Rules for Bits in Overlay (DWords 5, 6, 8 and 9)
DWord QH
Offset
Bit
Name
Description
5
0x14
4–1
NakCnt
Nak counter—RW. This field is a counter the host controller decrements
whenever a transaction for the endpoint associated with this queue head results
in a Nak or Nyet response. This counter is reloaded from RL before a transaction
is executed during the first pass of the reclamation list (relative to an
Asynchronous List Restart condition). It is also loaded from RL during an overlay.
6
0x18
31
dt
Data toggle. The Data Toggle Control controls whether the host controller
preserves this bit when an overlay operation is performed.
6
0x18
15
ioc
Interrupt on complete. The ioc control bit is always inherited from the source qTD
when the overlay operation is performed.
6 0x18
11–1
0
Cerr
Error counter. This two-bit field is copied from the qTD during the overlay and
written back during queue advancement.
6
0x18
0
Status[0]
Ping state (P)/ERR. If the EPS field indicates a high-speed endpoint, then this
field should be preserved during the overlay operation.
8 0x20
7–0
C-prog-mas
k
Split-transaction complete-split progress. This field is initialized to zero during any
overlay. This field is used to track the progress of an interrupt split-transaction.
9
0x24
11–5
S-bytes
The software must ensure that the S-bytes field in a qTD is zero before activating
the qTD. This field is used to keep track of the number of bytes sent or received
during an IN or OUT split transaction.
9
0x24
4–0
FrameTag
Split-transaction frame tag. This field is initialized to zero during any overlay. This
field is used to track the progress of an interrupt split-transaction.
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Offset
Normal Path Link Pointer
00
Typ
T
0x00
Back Path Link Pointer
00
Typ
T
0x04
Figure 24-42. Frame Span Traversal Node Structure
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
