Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
24-119
the endpoint if it is using a queue head. Maximum Length is defined as the minimum of Total Bytes to
Transfer and Maximum Packet Size. The Cerr field is not decremented for a packet babble condition (only
applies to queue heads). A babble condition also exists if IN transaction is in progress at High-speed EOF2
point. This is called a frame babble. A frame babble condition is recorded into the appropriate schedule
data structure. In addition, the host controller must disable the port to which the frame babble is detected.
The USBERRINT bit in the USBSTS register is set and if the USB Error Interrupt Enable bit in the
USBINTR register is set, then a hardware interrupt is signaled to the system at the next interrupt threshold.
The host controller must never start an OUT transaction that babbles across a micro-frame EOF.
NOTE
When a host controller detects a data PID mismatch, it must either: disable
the packet babble checking for the duration of the bus transaction or do
packet babble checking based solely on Maximum Packet Size. The USB
core specification defines the requirements on a data receiver when it
receives a data PID mismatch (for example, expects a DATA0 and gets a
DATA1 or visa-versa). In summary, it must ignore the received data and
respond with an ACK handshake, in order to advance the transmitter's data
sequence.The EHCI interface allows the system software to provide buffers
for a Control, Bulk or Interrupt IN endpoint that are not an even multiple of
the maximum packet size specified by the device. Whenever a device
misses an ACK for an IN endpoint, the host and device are out of
synchronization with respect to the progress of the data transfer. The host
controller may have advanced the transfer to a buffer that is less than
maximum packet size. The device re-sends its maximum packet size data
packet, with the original data PID, in response to the next IN token. In order
to properly manage the bus protocol, the host controller must disable the
packet babble check when it observes the data PID mismatch.
24.9.14.1.3
Data Buffer Error
This event indicates that an overrun of incoming data or a underrun of outgoing data has occurred for this
transaction. This would generally be caused by the host controller not being able to access required data
buffers in memory within necessary latency requirements. These conditions are not considered transaction
errors, and do not effect the error count in the queue head. When these errors do occur, the host controller
records the fact the error occurred by setting the Data Buffer Error bit in the queue head, iTD or siTD.
If the data buffer error occurs on a non-isochronous IN, the host controller will not issue a handshake to
the endpoint. This forces the endpoint to resend the same data (and data toggle) in response to the next IN
to the endpoint.
If the data buffer error occurs on an OUT, the host controller must corrupt the end of the packet so that it
cannot be interpreted by the device as a good data packet. Simply truncating the packet is not considered
acceptable. An acceptable implementation option is to 1's complement the CRC bytes and send them.
There are other options suggested in the Transaction Translator section of the
USB Specification
Revision 2.0
.
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
