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4. Initial default boot core that executes code from the Boot Assist Flash (BAF). Debuggers have access to this core initially

as well.

2 Differences between MPC57xx e200zx cores

The second major generation of the e200zx cores has minor variations for different devices. The following sections show all
of the devices in the MPC57xx family and the variations of the cores used in each device (and version). The core options
have been divided into three sections:

• Core instruction set and execution options (signal processing instruction options, saturated math instructions, floating

point type options, instruction issue option, lock-step option etc.).

• Core bus interface options (memory protection options, end-to-end error correction code options, crossbar bus width,

local memory options, and cache options)

• Core debug options (Nexus class, timestamp option, trace port width, and whether it has the fixed JTAG Nexus register

access sequence)

The tables in the following sections are arranged by core complexity. The e200z210 is the "simplest" core (feature-wise) and
with the e200z759 being the most complex.

2.1 e200zx core execution options

The first set of options that are available to be integrated into the cores instantiated into a particular MCU directly affect the
cores, including what instructions are supported and how the instructions execute. These options are shown in the following
table, then each of the options is explained in more detail.

Table 3. e200zx cores instruction differences

Device

Revision

Instantiation

Core Name

Book E

 

Dual Issue

Lockstep

General Purpose Registers

Signal Processing

Saturation

Floating Point

e200z210 based cores

MPC5748G

1.0

Core 2

e200z210n3

No

Single

No

32x32

No

No

No

e200z215 based cores

MPC5726L

1.0

Core 0

1

e200z215An3

No

Single

No

32x32

No

No

Scalar

e200z225 based cores

MPC5744K

1.0

Core 2

1

e200z225n3

No

Single

No

32x32

LSP

No

Scalar

MPC5744K

2.0

Core 2

1

e200z225Bn3

No

Single

No

32x32

LSP

Yes

Scalar

e200z410 based cores

MPC5746M

2.0

Core 0/1 e200z410n3

No

Single

Delayed

32x32

No

Yes

Scalar

MPC5744K

2.0

Core 0

e200z410Dn3

No

Single

Delayed

32x32

No

Yes

Scalar

Table continues on the next page...

Differences between MPC57xx e200zx cores

Qorivva MPC57xx e200zx Core Differences, Rev 0, 10/2013

Freescale Semiconductor, Inc.

3

Summary of Contents for MPC57xx

Page 1: ...nces and gives a basic summary of the feature this document does not fully explain the feature in detail The core reference manuals should be consulted for additional information The table below shows...

Page 2: ...step core can be disabled to save power however this is not a significant amount of power Table 2 MPC57xx core summary Device Revision Core 0 Core 1 Core 2 Lock Step core1 MPC5726L 12 e200z215An3 MPC...

Page 3: ...ture wise and with the e200z759 being the most complex 2 1 e200zx core execution options The first set of options that are available to be integrated into the cores instantiated into a particular MCU...

Page 4: ...s Scalar MPC5777M 2 0 MPC5744P 2 0 Core 0 e200z4251n3 No Dual Delayed 32x32 LSP No Scalar e200z710 based cores MPC5777M 2 0 Core 0 1 e200z710n3 No Single Delayed 32x32 No Yes Scalar e200z720 based cor...

Page 5: ...The Lightweight Signal Processing Unit LSP supports a limited number of basic math instructions to speed digital signal processing algorithms Signal Processing Extension SPE 1 1 The Signal Processing...

Page 6: ...4I 64D 32K 16K No 8K Future device 1 1 0 Core 0 1 e200z425n3 24 Yes 64I 64D 32K 16K No 8K Future device 1 2 0 Core 0 1 e200z425n3 24 Yes 64I 64D 32K 16K No 8K MPC5777M 1 0 Core 2 e200z425Bn3 24 Yes 64...

Page 7: ...local memory The local data memory allows for fast access of variables that are required frequently by a single core Local Instruction Memory ITCM Some cores support a fast local instruction memory S...

Page 8: ...0n3 3 No 30 Variable MPC5746M 1 0 1 1 Core 0 1 MPC5744P 1 0 Core 0 e200z4201n3 3 No 30 or 4 Fixed Fixed MPC5775K 1 0 1 1 2 0 Core 0 e200z4201n3 3 Yes buffered 30 or 16 Fixed Fixed MPC5748G 1 0 Core 1...

Page 9: ...s Aurora Router NAR as the Nexus output controller Devices that instantiate the Nexus Port Controller NPC use the buffered timestamps This difference is due to the minimal time that messages spend in...

Page 10: ...e Machine Reset In some cases the Nexus state machine in the e200zx core does not get properly reset when the JTAG TAP is changed to a different JTAG client to a different core or other client Previou...

Page 11: ...ithout limitation consequential or incidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual perfor...

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