Table 3. e200zx cores instruction differences (continued)
Device
Revision
Instantiation
Core Name
Book E
Dual Issue
Lockstep
General Purpose Registers
Signal Processing
Saturation
Floating Point
e200z420 based cores
MPC5744K
1.0
Core 0
e200z420n3
No
Dual
Delay
ver.
32x32
No
No
Scalar
MPC5746M
1.0/1.1 Core 0/1
MPC5744P
1.0
Core 0
e200z4201n3
No
Dual
Delay
ver.
32x32
No
No
Scalar
MPC5775K
1.0/1.1/
2.0
Core 0
e200z4201n3
No
Dual
Delay
ver.
32x32
No
No
Scalar
MPC5748G
1.0
Core
0
1
/1
e200z4204n3
No
Dual
No
32x32
No
No
Scalar
e200z425 based cores
MPC5746M
1.0
Core 2
1
e200z425n3
No
Dual
No
32x32
LSP
No
Scalar
Future device 1
1.0
Core
0/1
1
e200z425n3
No
Dual
Delayed
32x32
LSP
No
Scalar
Future device 1
2.0
Core
0/1
1
e200z425n3
No
Dual
Delayed
32x32
LSP
Yes
Scalar
MPC5777M
1.0
Core 2
1
e200z425Bn3
No
Dual
No
32x32
LSP
No
Scalar
MPC5746M
2.0
Core 2
1
e200z425Bn3
No
Dual
No
32x32
LSP
Yes
Scalar
MPC5777M
2.0
MPC5744P
2.0
Core 0
e200z4251n3
No
Dual
Delayed
32x32
LSP
No
Scalar
e200z710 based cores
MPC5777M
2.0
Core 0/1 e200z710n3
No
Single
Delayed
32x32
No
Yes
Scalar
e200z720 based cores
MPC5777M
1.0
Core 0/1 e200z720n3
No
Dual
Delayed
32x32
No
No
Scalar
e200z7260 based cores
MPC5775K
1.0/1.1/
2.0
Core 1/2 e200z7260n3
No
Dual
No
32x64
SPE2
No
Vector
e200z759 based cores
Future device 2
1.0
Core
0/1
1
e200z759n3
Yes
Dual
Delayed
32x64
SPE1.1
No
Vector
1. Initial boot core.
Book E Support - Previous e200z3 through e200z7 cores supported both the Power Architecture Book E instruction set and
a more size efficient Variable Length Encoded (VLE) instruction set. The previous e200z0 cores used on some of the
MPC5500 and MPC5600 devices supported only the VLE instruction set. Most of new MPC57xx devices support only the
VLE instruction set, however, there is at least one device planned in the future that will support the full Book E instruction
set.
Differences between MPC57xx e200zx cores
Qorivva MPC57xx e200zx Core Differences, Rev 0, 10/2013
4
Freescale Semiconductor, Inc.
