NXP Semiconductors MPC57xx Application Note Download | Manualshive

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Table 5. e200zx cores bus interface and memory options (continued)

Device

Revision

Instantiation

Core Name

MPU

e2eECC

XBAR Bus

DTCM

ITCM

D-cache

I-cache

MPC5748G

1.0

Core 0

e200z210n3

No

Yes

64I/64D

No

No

No

No

e200z215 based cores

MPC5726L

1.0

Core 0 e200z215An3

No

No

32I/32D

No

No

No

No

e200z225 based cores

MPC5744K

1.0

Core 2

e200z225n3

8

Yes

64I/64D

48K

16K

No

No

MPC5744K

2.0

Core 2 e200z225Bn3

8

Yes

64I/32D

48K

16K

No

No

e200z420 based cores

MPC5746M

2.0

Core 0/1 e200z410n3

24

Yes

64I/64D

64K

16K

4K

8K

MPC5744K

2.0

Core 0

e200z410Dn

3

24

Yes

64I/64D

64K

16K

2K

4K

e200z420 based cores

MPC5744K

1.0/1.1

Core 0

e200z420n3

24

Yes

64I/64D

64K

16K

4K

8K

MPC5746M

Core 0/1

MPC5744P

1.0

Core 0 e200z4201n3

24

Yes

64I/64D

64K

No

4K

8K

MPC5775K

1.0/1.1/

2.0

Core 2 e200z4201n3

24

Yes

64I/64D

64K

No

4K

8K

MPC5748G

1.0

Core 1/2 e200z4204n3

No

Yes

64I/64D

No

No

4K

8K

e200z425 based cores

MPC5746M

1.0

Core 2

e200z425n3

24

Yes

64I/64D

32K

16K

No

8K

Future device 1

1.0

Core 0/1 e200z425n3

24

Yes

64I/64D

32K

16K

No

8K

Future device 1

2.0

Core 0/1 e200z425n3

24

Yes

64I/64D

32K

16K

No

8K

MPC5777M

1.0

Core 2 e200z425Bn3

24

Yes

64I/32D

64K

16K

No

8K

MPC5746M

2.0

Core 2 e200z425Bn3

24

Yes

64I/32D

64K

16K

No

8K

MPC5777M

2.0

MPC5744P

2.0

Core 0 e200z4251n3

24

Yes

64I/64D

64K

No

4K

8K

e200z710 based cores

MPC5777M

2.0

Core 0/1 e200z710n3

24

Yes

64I/64D

64K

16K

4K

16K

e200z720 based cores

MPC5777M

1.0

Core 0/1 e200z720n3

24

Yes

64I/64D

64K

16K

4K

16K

e200z7260 based cores

MPC5775K

1.0/1.1/

2.0

Core 1/2 e200z7260n3

24

Yes

64I/64D

64K

No

16K

16K

e200z759 based cores

Future device 2

1.0

Core 0/1 e200z759n3

MMU

No

64I/64D

No

No

16K

16K

Memory Protection Unit (MPU) - The Memory Protection Unit (MPU) allows memory regions to be protected from being
accessed by certain cores, protected from being modified by certain cores, protected from core execution, for enabling or
disabling of being cached, and for other safety protection features.

Differences between MPC57xx e200zx cores

Qorivva MPC57xx e200zx Core Differences, Rev 0, 10/2013

6

Freescale Semiconductor, Inc.

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Summary of Contents for MPC57xx

Page 1: ...nces and gives a basic summary of the feature this document does not fully explain the feature in detail The core reference manuals should be consulted for additional information The table below shows...

Page 2: ...step core can be disabled to save power however this is not a significant amount of power Table 2 MPC57xx core summary Device Revision Core 0 Core 1 Core 2 Lock Step core1 MPC5726L 12 e200z215An3 MPC...

Page 3: ...ture wise and with the e200z759 being the most complex 2 1 e200zx core execution options The first set of options that are available to be integrated into the cores instantiated into a particular MCU...

Page 4: ...s Scalar MPC5777M 2 0 MPC5744P 2 0 Core 0 e200z4251n3 No Dual Delayed 32x32 LSP No Scalar e200z710 based cores MPC5777M 2 0 Core 0 1 e200z710n3 No Single Delayed 32x32 No Yes Scalar e200z720 based cor...

Page 5: ...The Lightweight Signal Processing Unit LSP supports a limited number of basic math instructions to speed digital signal processing algorithms Signal Processing Extension SPE 1 1 The Signal Processing...

Page 6: ...4I 64D 32K 16K No 8K Future device 1 1 0 Core 0 1 e200z425n3 24 Yes 64I 64D 32K 16K No 8K Future device 1 2 0 Core 0 1 e200z425n3 24 Yes 64I 64D 32K 16K No 8K MPC5777M 1 0 Core 2 e200z425Bn3 24 Yes 64...

Page 7: ...local memory The local data memory allows for fast access of variables that are required frequently by a single core Local Instruction Memory ITCM Some cores support a fast local instruction memory S...

Page 8: ...0n3 3 No 30 Variable MPC5746M 1 0 1 1 Core 0 1 MPC5744P 1 0 Core 0 e200z4201n3 3 No 30 or 4 Fixed Fixed MPC5775K 1 0 1 1 2 0 Core 0 e200z4201n3 3 Yes buffered 30 or 16 Fixed Fixed MPC5748G 1 0 Core 1...

Page 9: ...s Aurora Router NAR as the Nexus output controller Devices that instantiate the Nexus Port Controller NPC use the buffered timestamps This difference is due to the minimal time that messages spend in...

Page 10: ...e Machine Reset In some cases the Nexus state machine in the e200zx core does not get properly reset when the JTAG TAP is changed to a different JTAG client to a different core or other client Previou...

Page 11: ...ithout limitation consequential or incidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual perfor...

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