NXP Semiconductors MSC7110, Reference Manual

Page 1: ...ding a competitive price per channel for voice over packet systems Designed with attention to system requirements from the start the MSC711x family delivers one core architecture for digital signal pr...

Page 2: ...MSC711x Application Development System MSC711xADS Reference Manual Rev 1 2 Freescale Semiconductor...

Page 3: ...interfaces 128 channels each 10 100 Ethernet MAC 32 channel DMA controller AHB Lite internal bus DDR external memory controller interface 16 bit enhanced host port JTAG OCE10 emulator test Process Vol...

Page 4: ...4351 connected to the TSI Two PSTN connections using Legerity Le78D110VC Le77D11xVC SLIC SLAC connected to the TSI H 110 RS 232 universal asynchronous receiver transmitter UART port 9 pin D connector...

Page 5: ...tured MSC711x Development Kit Figure 1 2 MSC711xADS External Connections cPCI Backplane Connections PSTN Ports Fast Ethernet to MSC711x E1 T1 RS 232 JTAG OCE10 Parallel Port RS 232 Fast Ethernet to MP...

Page 6: ...MSC711xADS Documentation is available from a local Freescale distributor a Freescale semiconductor sales office or a Freescale Literature Distribution Center For documentation updates visit the Frees...

Page 7: ...ormation on the architecture and programming model of the OCE10 on chip emulator which is the StarCore implementation of the EOnCE The OCE10 on chip emulator is a peripheral that facilitates debugging...

Page 8: ...MSC711x Application Development System MSC711xADS Reference Manual Rev 1 8 Freescale Semiconductor Overview...

Page 9: ...o the JTAG COP header connector P14 b For a PC install the CodeWarrior test software or any other compatible debugging software on the PC The MSC711xADS is optimized for CodeWarrior test software 2 De...

Page 10: ...tor P11 with no use of an external JTAG command converter The debugging tool must support the shared JTAG chain option as CodeWarrior does In stand alone operation the host computer controls the MSC71...

Page 11: ...age 17 PCI expansion enable disable JP7 See Section 2 4 14 on page 17 Host MPC8272 enable disable JP8 See Section 2 4 15 on page 18 Figure 2 1 MSC711xADS Switch and Jumper Locations J1 J2 J4 J5 P2 P6...

Page 12: ...the ON position its related signal is deasserted to 0 When the switch is in the OFF position its related signal is asserted to 1 Figure 2 2 SW4 Factory Default Setting 2 4 3 MSC711x Event Pin Configu...

Page 13: ...ntrols whether the parallel port connection is forced In normal operation the hardware automatically identifies the connection of the parallel port On some computers this may not happen so this switch...

Page 14: ...t the EEPROM I2C bus address Switch 4 sets the write protection mode for the EEPROM Table 2 3 SW6 Settings Switch Type of Connection OFF ON 1 Chain select 1 1 0 2 Chain select 2 1 0 3 Force parallel p...

Page 15: ...3 set MODCK 1 3 respectively Switches 4 7 set MODCKH 0 3 respectively Switch 8 sets the PCIMODCK bit 2 4 7 Main Power Switch SW9 Switch 9 is the main power ON OFF switch Toggling the switch turns the...

Page 16: ...sition the TSI frame and clock signals are disconnected from the MSC711x The MSC711x can be the TDM master or an external master clock and frame sources can be connected through the J5 edge connector...

Page 17: ...reset to the MPC8272 processor When the hard resets are disconnected the MPC8272 and the MSC711x processors have separate hard reset signals that do not affect each other In the normal 1 2 position t...

Page 18: ...tly of the MPC8272 state Figure 2 12 JP8 Host Enable 2 5 MSC711xADS Boot MSC711x devices can boot from the HDI16 bus or from an external EEPROM with a serial I2C interface The MSC711xADS uses a serial...

Page 19: ...START condition which is generated by the bus master The START condition is followed by a device select code and RW bit see Figure 2 14 It is terminated by an acknowledge bit that is inserted by the m...

Page 20: ...all data residing in volatile memories are lost SW10 MPC8272 soft reset Generates a soft reset to the MPC8272 The soft reset switch signal is debounced SW11 MPC8272 hard reset Generates a hard reset t...

Page 21: ...4 Memory Map Programming Model on page 29 controls the state of LD19 LD1 MSC711x fast Ethernet port enabled Yellow The fast Ethernet port PHY the DM9161 is connected to the MSC711x When this LED is n...

Page 22: ...to the PC parallel port in SPP mode and the COP JTAG connector P14 is irrelevant LD21 Parallel port connection in EPP mode Green The board is connected directly to the PC parallel port in EPP Mode an...

Page 23: ...ock Mode Settings SW8 on page 15 After deassertion of power on reset the hard reset sequence starts During the hard reset sequence many options are configured Some of these options are additional cloc...

Page 24: ...HRESET may cause permanent damage to either board logic and or to the MPC8272 and the MSC711x processors To prevent contention always drive HRESET with an open drain gate When a hard reset is applied...

Page 25: ...The MSC711x processor requires a reference clock input CLKIN by which the clock synthesis module in the MSC711x core generates all the timings needed The recommended CLKIN frequency is 20 MHz As Figur...

Page 26: ...2 bit IPBus CLKIN AHB Clock to Crossbar Switch DMA to 32 Bit Watchdog Timer TDM Peripheral to TDM Clock Frame Sync EVNT Event Port MUX MUX UART to UART Tx Rx M2 Boot ROM CPU 3 SC1400 Core DIV 1 to 25...

Page 27: ...40 mA for the SSTL_IO DDR at 2 5 V 511 mA for the core at 1 2 V The MSC711xADS has three distinct power supplies 1 2 V core 2 5 V DDR I O and 3 3V standard I O When the board is powered up or powered...

Page 28: ...that is at least 0 7 V less than that of the 3 3 V supply Also at any instant the 1 2 V supply must maintain a voltage that is at least 0 7 V less than that of the 2 5 V supply Figure 3 5 Power Suppl...

Page 29: ...e controlled by the MPC8272 memory controller Therefore the memory map is reprogrammable After a hard reset the debugger checks for the size delay and type of the Flash memory on the board and program...

Page 30: ...10 0x04500014 0x04500018 0x0450001C BCSR 0 7 BCSR0 BCSR1 BCSR2 BCSR3 BCSR4 BCSR5 BCSR6 BCSR7 32 Bits 32 KB 4 Bytes 4 Bytes 4 Bytes 4 Bytes 4 Bytes 4 Bytes 4 Bytes 4 Bytes 0x04508000 0x045FFFFF Empty s...

Page 31: ...5 26 27 28 29 30 31 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 1 BCSR0 Bit Descriptions Bit Reset Value Description Settings PQETHEN 0 0 MPC8272 Ethernet enable 0 Disabled 1 Enabled PQETHRST...

Page 32: ...RESET 0 Table 4 2 BCSR1 Bit Descriptions Bit Reset Value Description Settings BVER0 0 0 Board version 0 00 Prototype 01 Pilot 10 Rev A 11 Rev B BVER1 1 0 Board version 1 PCIEN 2 0 PCI enable HDI disab...

Page 33: ...3 BCRS2 Bit Descriptions Bit Reset Value Description Setting H8B 0 0 MSC711xADS HDI 8 Bit mode 0 16 bit HDI mode 1 8 bit HDI mode DBREQ 1 0 MSC711xADS debug mode request 0 Normal run mode 1 Debug mod...

Page 34: ...BCSR3 Bit Descriptions Bit Reset Value Description Settings SLETHEN 0 0 MSC711x fast Ethernet port enable 1 Enable 0 Disable MIITDM2EN 1 0 MSC711xADS MII TDM2 port 0 MII TDM2 enable 1 MII TDM2 disable...

Page 35: ...18 19 20 21 22 23 24 25 26 27 28 29 30 31 TYPE R RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3 3 BCRS4 Bit Descriptions Bit Reset Value Description Function SYSEN 0 1 MSC711xADS is in cPCI rack 0 Sys...

Page 36: ...ard Control Status Registers 5 7 Offset 0x14 BCSR 5 7 are accessed at offset 0x14 from the BCSR base address They are read only registers that can be read at any time Table 3 4 BCRS 5 7 Bit Descriptio...

Page 37: ...o two banks External host register bank that is accessible to an external host Chip register bank that is accessible to the MSC711x device The HDI16 supports two classes of interfaces to external devi...

Page 38: ...cable Figure 5 1 shows the connecting signals and the pinout of the connector Table 5 1 describes the connector pins Figure 5 1 HDI16 Bus Connection to the Host Processor Header HDI Header MSC711x HD...

Page 39: ...Reserved 25 HCS1 I Host Chip Select 1 The HDI CS is determined by the logical OR between HCS1 and HCS2 26 HCS2 I Host Chip Select 2 The HDI CS is determined by the logical OR between HCS1 and HCS2 27...

Page 40: ...r s responsibility to prevent such errors 5 3 MSC711x Connection to the MPC8272 Figure 5 2 shows the data and signal connections between the MSC711x device and the host MPC8272 The data and address li...

Page 41: ...SC711x The RS 232 connection to the MSC711x processor occurs via a MAX3241 transceiver that generates the required RS 232 levels using a single 3 3 V supply The transceiver is always enabled The RS 23...

Page 42: ...whether a terminal is connected to the MSC711xADS board DSR O Data set ready This line is always asserted by the MSC711xADS RTS I Request to send This line is not connected in the MSC711xADS CTS O Cl...

Page 43: ...5 6 JTAG OCE10 Port Connector Table 5 2 JTAG OCE10 Pins Pin Signal Attribute Description 1 TDI I Transmit Data In The JTAG serial data input of the ADS sampled on the rising edge of TCK 2 GND P Digita...

Page 44: ...al mode serial boot ROM connected to the CPU 5 6 DDR SDRAM Interface The MSC711x external memory interface has a maximum capacity of 32 bits but the most common DDR SDRAM device has a capacity of only...

Page 45: ...face MII It also supports reduced MII RMII The MPC8272 processor works only in MII mode but the MSC711x port can be switched between the MII and RMII modes The DM9161 uses a low power high performance...

Page 46: ...om the MPC8272 60x bus Four MT48LC8M16A2 by Micron memory devices or compatibles implement the SDRAM Each memory device is 2 M 16 4 banks The SDRAM timing is controlled by SDRAM machine 1 which is ass...

Page 47: ...mode register through the SDRAM address lines The MPC8272 SDRAM machine fully supports this command Before the SDRAM can be programmed the MPC8272 SDRAM machine must be initialized Table 5 3 shows th...

Page 48: ...to select the Flash memory Flash memory can be disabled 1 or enabled 0 at any time by writing to the FlashEn bit in BCSR1 Figure 5 10 shows the Flash memory connection scheme The access time of the M...

Page 49: ...ammable on each of the 32 physical streams which are selected in groups of four The data rates are on a per stream basis as follows 2 048 Mbps and 4 096 Mbps 8 192 Mbps and 16 384 Mbps After buffering...

Page 50: ...criber line circuitry in a digital switch These functions involve converting an analog voice signal into digital PCM samples and converting digital PCM samples back into an analog signal During conver...

Page 51: ...on Development System MSC711xADS Reference Manual Rev 1 Freescale Semiconductor 51 Figure 5 12 E1 T1 Framer Connection RJ45 TDM Bus to TSI BADD 23 31 Controls BDAT 0 7 PMC PM4351 NI Framer Magnetic 1...

Page 52: ...any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims c...