MSC711x Application Development System (MSC711xADS) Reference Manual, Rev. 1
16
Freescale Semiconductor
Hardware Configuration and Boot
2.4.9
H.110 Back Plane Reset (JP2)
JP2 selects the connection of the MSC711x hard reset to the H.110 back plane.
• When placed, the MSC711x hard reset is connected to the H.110 back plane reset.
• When not placed, the MSC711x hard reset is disconnected from the H.110 back plane reset.
Figure 2-6. JP2, Hard Rest Back Plane
2.4.10 TDM Master Selection (JP3)
JP3 selects the master (clock and frame source) of the TDM channels of the MSC711x.
• In the TSI (1-2) position, the TSI is the TDM master (factory default).
• In the external (2-3) position, the TSI frame and clock signals are disconnected from the MSC711x. The
MSC711x can be the TDM master or an external master (clock and frame sources) can be connected through the
J5 edge connector.
Figure 2-7. JP3, TSI TDM Master
2.4.11 MSC711x Clock In Source (JP4)
JP4 selects the source for the clock-in input of the MSC711x.
• In the external (1-2) position, the clock-in source is the SMB connector (P9) and the external clock generator
must be used.
• In the oscillator (2-3) position, the clock-in source is the on-board oscillator (S2).
Figure 2-8. JP4, Clock Input setting
Note:
For the mode change to occur, JP4 should be set while the board is powered OFF.
1
2
1
2
Hard Reset Connected to Back Plane
Factory Default
Hard Reset Disconnected from Back Plane
JP2
1
2
3
1
2
3
TSI
External
Factory Default
JP3
1
2
3
1
2
3
External
Oscillator
Factory Default
JP4
