UM10147_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 28 April 2008
61 of 134
NXP Semiconductors
UM10147
P89LPC952/954 User manual
Table 54.
Serial Port modes
SM0_n, SM1_n
UART mode
UART baud rate
00
Mode 0: shift register
CCLK
⁄
16
(default mode on any reset)
01
Mode 1: 8-bit UART
Variable (see
10
Mode 2: 9-bit UART
CCLK
⁄
32
or
CCLK
⁄
16
11
Mode 3: 9-bit UART
Variable (see
Table 55.
Serial Port 0 Status register (S0STAT - address BAh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
DBMOD
_0
INTLO_0 CIDIS_0
DBISEL_
0
FE_0
BR_0
OE_0
STINT_0
Reset
x
x
x
x
x
x
0
0
Table 56.
Serial Port 0 Status register (S0STAT - address BAh) bit description
Bit Symbol
Description
0
STINT_0 Status Interrupt Enable 0 . When set = 1, FE_0, BR_0, or OE_0 can cause an
interrupt. The interrupt used (vector address 0023h) is shared with RI (CIDIS = 1)
or the combined TI/RI (CIDIS = 0). When cleared = 0, FE_0, BR_0, OE_0 cannot
cause an interrupt. (Note: FE_0, BR_0, or OE_0 is often accompanied by a RI_0,
which will generate an interrupt regardless of the state of STINT_0). Note that
BR_0 can cause a break detect reset if EBRR (AUXR1.6) is set to logic 1.
1
OE_0
Overrun Error 0 flag is set if a new character is received in the receiver buffer while
it is still full (before the software has read the previous character from the buffer),
i.e., when bit 8 of a new byte is received while RI_0 in S0CON is still set. Cleared
by software.
2
BR_0
Break Detect 0 flag. A break is detected when any 11 consecutive bits are sensed
low. Cleared by software.
3
FE_0
Framing error 0 flag is set when the receiver fails to see a valid STOP bit at the
end of the frame. Cleared by software.
4
DBISEL
_0
Double buffering transmit interrupt select 0. Used only if double buffering is
enabled. This bit controls the number of interrupts that can occur when double
buffering is enabled. When set, one transmit interrupt is generated after each
character written to S0BUF, and there is also one more transmit interrupt
generated at the beginning (INTLO_0 = 0) or the end (INTLO_0 = 1) of the STOP
bit of the last character sent (i.e., no more data in buffer). This last interrupt can be
used to indicate that all transmit operations are over. When cleared = 0, only one
transmit interrupt is generated per character written to S0BUF. Must be logic 0
when double buffering is disabled. Note that except for the first character written
(when buffer is empty), the location of the transmit interrupt is determined by
INTLO_0. When the first character is written, the transmit interrupt is generated
immediately after S0BUF is written.
5
CIDIS_0 Combined Interrupt Disable 0. When set = 1, Rx and Tx interrupts are separate.
When cleared = 0, the UART uses a combined Tx/Rx interrupt (like a conventional
80C51 UART). This bit is reset to logic 0 to select combined interrupts.
6
INTLO_
0
Transmit interrupt position 0. When cleared = 0, the Tx interrupt is issued at the
beginning of the stop bit. When set = 1, the Tx interrupt is issued at end of the stop
bit. Must be logic 0 for mode 0. Note that in the case of single buffering, if the Tx
interrupt occurs at the end of a STOP bit, a gap may exist before the next start bit.
7
DBMOD
_0
Double buffering mode 0. When set = 1 enables double buffering. Must be logic 0
for UART mode 0. In order to be compatible with existing 80C51 devices, this bit is
reset to logic 0 to disable double buffering.
