NXP Semiconductors PCAL6524EV, User Manual

NXP Semiconductors

UM11711

PCAL6524EV-ARD evaluation board

PCAL6524

(U1) pin

Direction

CPLD

(U2) pin

LED

Switch

16 BIT – I/O PORT (J6)

8 BIT – I/O PORT (J7)

P0_3

I/O

IO_12

-

-

6

-

P0_4

I/O

IO_13

-

-

7

-

P0_5

I/O

IO_14

-

-

8

-

P0_6

I/O

IO_15

-

-

9

-

P0_7

I/O

IO_16

-

-

10

-

P1_0

I/O

IO_17

-

-

11

-

P1_1

I/O

IO_18

-

-

12

-

P1_2

I/O

IO_19

-

-

13

-

P1_3

I/O

IO_22

-

-

14

-

P1_4

I/O

IO_23

-

-

15

-

P1_5

I/O

IO_24

-

-

16

-

P1_6

I/O

IO_25

-

-

17

-

P1_7

I/O

IO_26

-

-

18

-

P2_0

Output

-

D5

-

-

2

P2_1

Output

-

D6

-

-

3

P2_2

Output

-

D7

-

-

4

P2_3

Output

-

D8

-

-

5

P2_4

Output

-

-

SW1

-

6

P2_5

Output

-

-

SW2

-

7

P2_6

Output

-

-

SW3

-

8

P2_7

Output

-

-

SW4

-

9

Table 2. I/O allocation

...continued

The on- board LEDs can be disabled by placing JP2 jumper in 2-3 position (OPTION

1, see SPF-46658.pdf file). This feature is useful when the user uses the board with

external device connected to J7 I/O port. The switches are connected to the bus through

620-ohm series resistors (R49 – R52), to avoid bus conflict (short-circuit if the line is set

accidentally as output and the switch is pressed).

4.9 CPLD

The PCAL6524EV-ARD board contains a MAX V series CPLD from Intel/Altera (U2,

5M80ZE64C5N). The role of this IC is decoder / driver for the on-board four-digit LED

display (D9 to D12). The CPLD works as signal bridge between the ports P0 and P1

of the PCAL6524 IC and the LED displays. Additionally, a six-line control bus is linked

between the MAX V IC and the Arduino port. For details, see SPF-46658.pdf schematic

file of PCAL6524EV-ARD daughterboard. The internal firmware of the MAX V CPLD is

controlled from the GUI application through the control bus. The CPLD control bus sets

the operation modes of MAX V CPLD. The MAX_CLK line is not used (IO_5/CLK0 pin of

U2 is masked). 

Table 3

 details the operation modes and the corresponding logic states of

CPLD control bus.

UM11711

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2022. All rights reserved.

User manual

Rev. 1.0 — 19 January 2022

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