NXP Semiconductors PCAL6524EV, User Manual

NXP Semiconductors

UM11711

PCAL6524EV-ARD evaluation board

4.6 I

2

C-bus

The PCAL6524EV-ARD board communicates with the host through an I

2

C-bus (pin

A3 – SCL, pin A2 – SDA). The communication provides internal configuration of the I/

O expander, reads the logic levels of the I/O pins configured as inputs, and sets the

logic level on the I/O pins configured as outputs. The internal configuration of the DUT

includes: direction of the digital I/O lines (input or output), polarity inversion, pull-up /

pull-down resistor enable, output strength, output configuration (push-pull or open-

drain), input latch configuration, interrupt register. The transaction speed of the I

2

C-bus

is compliant with Standard-mode (100kHz), Fast-mode (400kHz), and Fast-mode plus

(1MHz). For more details about I

2

C description and bus transactions, see PCAL6524

datasheet (NXP Semiconductors). The pull-up resistors of the I

2

C-bus are R43 and R44

(see SPF-46658.pdf schematic file).

4.7 Control bus

The control bus manages RESET, ADDR, and INT pins of the PCAL6524 IC. The

RESET pin is digital input and is controlled by the system host. Its role is to reset the I/

O expander when a time-out or other improper operation occurs. Asserting a low level of

this line forces a reset operation of the internal control section of the IC (puts the internal

registers in their default state and force a re-initialization of the I

2

C state machine, in

the same manner as power-on sequence). The RESET pin is controlled by the EVK

motherboard through J3-1 (ARDUINO port).
The ADDR pin is digital input and represents a programmable hardware address

package which can be asserted low or high, to assign two different slave addresses. The

input is controlled by the EVK through J3-2 (Arduino port).
The INT pin is an open-drain interrupt output, activated when any input state differs from

its corresponding input port register state, indicating to the host system that an input

state has changed. The line is monitored by the EVK through J3-3 ARDUINO port and

locally by the LED (D4) located on the daughterboard. The LED D4 can be deactivated

by removing JP1 jumper. When D4 is inactive (JP1 removed) the open-drain is polarized

through R42. R42 also has the role to compensate the voltage drop of D4 assuring 3.3V

high level in high state of the interrupt line (see SPF-46658.pdf schematic file).

4.8 I/O bus

The PCAL6524 IC contains 24 configurable I/O pins, organized in three ports, P0, P1,

and P2. All three ports are 8-bit wide. P0 and P1 are allocated to the four-digit LED

display (through MAX V CPLD, U2). The on-board LEDs (D5 to D8) and user switches

SW1 to SW4 are connected to port P2. All I/O lines of the PCAL6524 IC are linked to

the I/O port connectors for external access of the I/O lines (see the schematic file of the

PCAL6524EV-ARD daughterboard). 

Table 2

 shows the allocation of the PCAL6524 I/O

lines (U1).

PCAL6524

(U1) pin

Direction

CPLD

(U2) pin

LED

Switch

16 BIT – I/O PORT (J6)

8 BIT – I/O PORT (J7)

P0_0

I/O

IO_9

-

-

3

-

P0_1

I/O

IO_10

-

-

4

-

P0_2

I/O

IO_11

-

-

5

-

Table 2. I/O allocation

UM11711

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© NXP B.V. 2022. All rights reserved.

User manual

Rev. 1.0 — 19 January 2022

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